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ADV8005 Hardware Reference Manual UG-707
5.6. VIDEO FIFO
The ADV8005 contains a FIFO located after the TMDS decoding block (refer to Figure 92 ). Data arriving into the Serial Video Rx will be at 1X
rate for non deep color modes (8-bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively). Data unpacking
and data rate reduction must be performed on the incoming data to provide the
ADV8005 digital core with the correct data rate and data bit
width. The video FIFO is used to pass data safely across the clock domains.
Figure 92: HDMI Video FIFO
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are about
to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of FIFO control
and status registers described below.
dcfifo_level[2:0] , HDMI RX Map, Address 0xE21C[2:0] (Read Only)
This signal is a readback to indicate the distance between the read and write pointers. Overflow and underflow will read as level 0. The ideal
centered functionality will read as 0b100.
Function
dcfifo_level[2:0] Description
000 (default) FIFO has underflowed or overflowed
001 FIFO is about to overflow
010 FIFO has some margin
011 FIFO has some margin
100 FIFO perfectly balanced
101 FIFO has some margin.
110 FIFO has some margin.
111 FIFO is about to underflow
dcfifo_locked
, HDMI RX Map, Address 0xE21C[3] (Read Only)
This bit is a readback to indicate if the Video FIFO is locked.
Function
dcfifo_locked Description
0 (default) Video FIFO is not locked. Video FIFO had to resynchronize between previous two Vsyncs
1 Video FIFO is locked. Video FIFO did not have to resynchronize between previous two Vsyncs
dcfifo_recenter
, HDMI RX Map, Address 0xE25A[2] (Self-Clearing)
This bit is used as a reset to recenter the Video FIFO. This is a self clearing bit.
Function
dcfifo_recenter Description
0 (default) Video FIFO normal operation.
1 Video FIFO to re-centre.
+
-
T M D S
C lo c k
+
-
T M D S
C h a n n e l 0
+
-
+
-
T M D S
P L L
T M D S
S a m p lin g
a n d
D a ta
R e c o v e r y
T M D S C h 2
1 0
1 0
1 0
D iv id e r
D P L L
F IF O
T M D S
C h a n n e l 1
T M D S
C h a n n e l 2
T M D S C h 1
T M D S C h 0
T M D S
D e c o d in g
1 2
1 2
1 2
R
G
B
H S
V S
D E
1 2
1 2
1 2
R
G
B
H S
V S
D E
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