UG-707
ADV8005 Hardware Reference Manual
Packet Map Address
Access Type
Register Name
Default Value
Byte Name
0xF3E6
R/W
spare4_pb3[7:0]
0b00000000
Data Byte 3
0xF3E7
R/W
spare4_pb4[7:0]
0b00000000
Data Byte 4
0xF3E8
R/W
spare4_pb5[7:0]
0b00000000
Data Byte 5
0xF3E9
R/W
spare4_pb6[7:0]
0b00000000
Data Byte 6
0xF3EA
R/W
spare4_pb7[7:0]
0b00000000
Data Byte 7
0xF3EB
R/W
spare4_pb8[7:0]
0b00000000
Data Byte 8
0xF3EC
R/W
spare4_pb9[7:0]
0b00000000
Data Byte 9
0xF3ED
R/W
spare4_pb10[7:0]
0b00000000
Data Byte 10
0xF3EE
R/W
spare4_pb11[7:0]
0b00000000
Data Byte 11
0xF3EF
R/W
spare4_pb12[7:0]
0b00000000
Data Byte 12
0xF3F0
R/W
spare4_pb13[7:0]
0b00000000
Data Byte 13
0xF3F1
R/W
spare4_pb14[7:0]
0b00000000
Data Byte 14
0xF3F2
R/W
spare4_pb15[7:0]
0b00000000
Data Byte 15
0xF3F3
R/W
spare4_pb16[7:0]
0b00000000
Data Byte 16
0xF3F4
R/W
spare4_pb17[7:0]
0b00000000
Data Byte 17
0xF3F5
R/W
spare4_pb18[7:0]
0b00000000
Data Byte 18
0xF3F6
R/W
spare4_pb19[7:0]
0b00000000
Data Byte 19
0xF3F7
R/W
spare4_pb20[7:0]
0b00000000
Data Byte 20
0xF3F8
R/W
spare4_pb21[7:0]
0b00000000
Data Byte 21
0xF3F9
R/W
spare4_pb22[7:0]
0b00000000
Data Byte 22
0xF3FA
R/W
spare4_pb23[7:0]
0b00000000
Data Byte 23
0xF3FB
R/W
spare4_pb24[7:0]
0b00000000
Data Byte 24
0xF3FC
R/W
spare4_pb25[7:0]
0b00000000
Data Byte 25
0xF3FD
R/W
spare4_pb26[7:0]
0b00000000
Data Byte 26
0xF3FE
R/W
spare4_pb27[7:0]
0b00000000
Data Byte 27
6.7.
SYSTEM MONITORING
6.7.1.
General Status and Interrupts
The
utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt and
status are listed in
, and
for details on the use of Tx interrupts.
Table 50: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0xEC96
Bit Name
Bit Position
Description
hdcp_authenticated_int
1 (Second LSB)
When set to 1 it indicates that HDCP/EDID state machine transitioned from state 3 to state 4.
Once set, it remains high until it is cleared by setting it to 1.
edid_ready_int
2
When set to 1 it indicates that EDID has been read from Rx and is available in Packet Map.
Once set, it remains high until it is cleared by setting it to 1.
vsync_int
5
When set to 1 it indicates that leading edge detected on VSync input to Tx core. Once set, it
remains high until it is cleared by setting it to 1.
rx_sense_int
6
When set to 1 it indicates that TMDS clock lines voltage has crossed 1.8 V from high to low
or low to high. Once set, it remains high until it is cleared by setting it to 1.
hpd_int
7
When set to 1 it indicates that transition for high to low or low to high was detected on
input HPD signal. Once set, it remains high until it is cleared by setting it to 1.
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