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ADV8005 Hardware Reference Manual

UG-707

1.3.

PROTOCOL FOR MAIN I

C PORT

The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains
high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits
(7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds
by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this
point and maintain an idle condition.

In the idle condition, the device monitors the SDA and SCL lines for the start condition and the correct transmitted address. The R/W bit
determines the direction of the data. A logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A logic
1 on the LSB of the first byte means that the master will read information from the peripheral.

The

ADV8005

has a single 8-bit I

C slave address. All register maps within the

ADV8005

can be accessed through this I

C address through 16-

bit addressing and 8-bit data registers. The

ADV8005

acts as a standard slave device on the I

C bus. It interprets the first byte as the I

C address

and the second byte and third bytes as the appropriate subaddress. The fourth byte is then considered the data for this subaddress register. This
means that I

C writes to the part will be in the form <I

C Address>, <Address MSBs>, <Address LSBs>, <Data>.

For example, to write 0xFF to the encoder register map, register 0x59AF, the I

C writes needed are 0x1A, 0x59, 0xAF, 0xFF. The addresses are

outlined in

Table 2

Figure 7

shows the register map architecture for the

ADV8005

Table 2:

ADV8005

C Address and Register Address Range for Different HW Blocks

Register Map Name

C Address

Register Address

IO Map

0x1A (0x18 with LSB low)

0x1A00 to 0x1BFF

Primary VSP Map

0xE800 to 0xE8FF

Primary VSP Map 2

0xE900 to 0xE9FF

Secondary VSP Map

0xE600 to 0xE6FF

Rx Main Map

0xE200 to 0xE2FF

Rx InfoFrame Map

0xE300 to 0xE3FF

Tx1 Main Map

0xEC00 to 0xECFF

Tx1 EDID Map

0xEE00 to 0xEEFF

Tx1 UDP Map

0xF200 to 0xF2FF

Tx1 Test Map

0xF300 to 0xF3FF

Tx2 Main Map

0xF400 to 0xF4FF

Tx2 EDID Map

0xF600 to 0xF6FF

Tx2 UDP Map

0xFA00 to 0xFAFF

Tx2 Test Map

0xFB00 to 0xFBFF

Encoder Map

0xE400 to 0xE4FF

DPLL Map

0xE000 to 0xE0FF

Figure 7: Register Map Architecture

It is possible to use the subaddresses auto-increment feature, which allows data to be accessed from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update
all the registers.

MAP

0x1A00 TO

0x1BFF

0xE800 TO

0xE8FF

0xE600 TO

0xE6FF

DPLL

MAP

0xE000 TO

0xE0FF

Rx MAIN