Analog Devices ADV8005, Справочник по аппаратуре

Страница: 68 / 317

UG-707 ADV8005 Hardware Reference Manual
from 1080p30 to 720p59.94 with frame tracking enabled, the resulting output may be 720p60 due to the 1:2 relationship.
Frame rate tracking is primarily intended for cases where the input frame rate and output frame rate have a 1:1 relationship or are close to this
target, that is, 59.94 Hz to 60 Hz. However, it can also be used for some standard frame rate conversion modes such as 24 Hz to 60 Hz, 25 Hz to
50 Hz, and 30 Hz to 60 Hz. The list of scaling conversions where frame tracking can be enabled is covered in
Table 5 .
Table 5: Frame Tracking
Output Frame Rate
In
p
u
t F
ra
m
e R
at
e
23.97 Hz 24 Hz 25 Hz 29.97 Hz 30 Hz 50 Hz 59.94 Hz 60 Hz
23.97 Hz Yes Yes No No No No Yes Yes
24 Hz Yes Yes No No No No Yes Yes
25 Hz No No Yes No No Yes No No
29.97 Hz No No No Yes Yes No Yes Yes
30 Hz No No No Yes Yes No Yes Yes
50 Hz No No Yes No No Yes No No
59.94 Hz Yes Yes No Yes Yes No Yes Yes
60 Hz Yes Yes No Yes Yes No Yes Yes
pvsp_track_en is set to enable frame tracking for the PVSP. svsp_track_en is set to enable frame tracking for the SVSP. If tracking is to be used
in frame rate conversion mode, video_in_id[7:0] , pvsp_autocfg_output_vid[7:0] (PVSP) and svsp_autocfg_output_vid[7:0] (SVSP) should also
be set.
pvsp_track_en , IO Map, Address 0x1A44[6]
This bit is used to enable tracking of the frequency error to reduce the number of dropped/repeated frames for the Primary VSP.
Function
pvsp_track_en Description
0 (default) Do not adjust for frequency difference between input and output vertical sync
1 Adjust for frequency difference between input and output vertical sync
svsp_track_en , IO Map, Address 0x1A44[2]
This bit is used to enable tracking of the frequency error to reduce the number of dropped/repeated frames for the Secondary VSP.
Function
svsp_track_en Description
0 (default) Do not adjust for frequency difference between input and output vertical sync
1 Adjust for frequency difference between input and output vertical sync
pvsp_err_sel , IO Map, Address 0x1A4E[3]
This bit is used to choose between phase locked loop and frequency locked loop for the Primary VSP frame tracking mode.
Function
pvsp_err_sel Description
0 (default) Phase error
1 Frequency error
svsp_err_sel , IO Map, Address 0x1A4F[3]
This bit is used to choose between phase locked loop and frequency locked loop for the Secondary VSP frame tracking mode.
Function
svsp_err_sel Description
0 (default) Phase error
1 Frequency error
2.2.5. DDR2 Interface
The ADV8005 uses DDR2 memory to enable the de-interlacer, scaler and OSD features. The DDR2 interface on ADV8005 is designed to meet
the JESD79-2F standard.
Rev. A | Page 68 of 317