Analog Devices ADV8005, Справочник по аппаратуре

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ADV8005 Hardware Reference Manual UG-707
6. HDMI TRANSMITTER
The HDMI transmitters on the ADV8005 are capable of outputting video data at up to 3 GHz and support 3D video output, ARC (common
mode only), and audio output.
The dual transmitter variants of
ADV8005 are the following:
•
ADV8005KBCZ-8A
•
ADV8005KBCZ-8N
•
ADV8005KBCZ-8C
The single transmitter variant of the
ADV8005 is the ADV8005KBCZ-8B.
Figure 95: Functional Block Diagram of HDMI Tx Core
As the two ADV8005 HDMI transmitters can be configured independently, there are separate register maps for both the HDMI Tx1 and HDMI
Tx2. The addresses for these register maps are listed in Table 42 .
Table 42: HDMI Transmitter Memory Addresses
Register Map Register Map Address
HDMI Tx1 Main Map 0xEC00 – 0xECFF
HDMI Tx1 EDID Map 0xEE00 – 0xEEFF
HDMI Tx1 UDP Map 0xF200 – 0xF2FF
HDMI Tx1 Test Map 0xF300 – 0xF3FF
HDMI Tx2 Main Map 0xF400 – 0xF4FF
HDMI Tx2 EDID Map 0xF600 – 0xF6FF
HDMI Tx2 UDP Map 0xFA00 – 0xFAFF
HDMI Tx2 Test Map 0xFB00 – 0xFBFF
While this chapter only references one instance of each HDMI Tx Map, the controls referenced are valid for both HDMI Tx1 and HDMI Tx2
register maps. The same register bits and controls as per
Table 42 apply for both transmitters.
6.1. GENERAL CONTROLS
To operate the HDMI Tx core, it is necessary to monitor the Hot Plug Detect (HPD) signal from the downstream sink and power up the Tx core
after the appropriate HPD becomes high. To power up the Tx core,
system_pd must be programmed to 0 when the HPD_TX1 pin is high. The
status of the HPD_TX1 pin is provided via hpd_state .
TX
Packet Builder
TX_0
Tx
Audio Receiver
Tx
HDCP
Encryption
Tx
HDCP
Keys
Tx
HDMI Encode
TX_1
TX_2
TX_C
AUD_IN [5:0]
MCLKIN
Data [35:0]
HS
VS
DE
Video_data [23:0]
HS
VS
DE
Tx Video Path
Tx
TMDS PLL
Serializer and
Drivers
c
lk
_
o
u
t
c
lk
_
d
a
ta
Audio_data [8:0]
Video_data
[23:0]
Audio_data
Video _data
[23:0]
Audio_data [8:0]
Ch0 [9:0]
Ch1 [9:0]
Ch2 [9:0]
DEEP
COLOR
CONV
Simplified
444 -> 422
Format
Detect
Black
level
enable
Pixel
repitition
HS
VS
VIC code
I2C
PLL m
PLL n
AVI _vid
[8:0]
SCLK
TX
Packet Builder
TX_0
Tx
Audio Receiver
Tx
HDCP
Encryption
Tx
HDCP
Keys
Tx
HDMI Encode
TX_1
TX_2
TX_C
AUD_IN [5:0]
MCLKIN
Data [35:0]
HS
VS
DE
Video_data [23:0]
HS
VS
DE
Tx Video Path
Tx
TMDS PLL
Serializer and
Drivers
c
lk
_
o
u
t
c
lk
_
d
a
ta
Audio_data [8:0]
Video_data
[23:0]
Audio_data
Video _data
[23:0]
Audio_data [8:0]
Ch0 [9:0]
Ch1 [9:0]
Ch2 [9:0]
DEEP
COLOR
CONV
Simplified
444 -> 422
Format
Detect
Black
level
enable
Pixel
repitition
HS
VS
VIC code
I2C
PLL m
PLL n
AVI _vid
[8:0]
SCLK
Rev. A | Page 197 of 317