Analog Devices ADV8005, Справочник по аппаратуре

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UG-707 ADV8005 Hardware Reference Manual
Table 60: Valid Configuration for audioif_sf[2:0] Address B8 (Main), Address 0x74[4:2]
audio_input_sel Value audioif_sf Value Options Corresponding Configuration
≠0b010
0b000 Not DSD Audio
0b010
0b001 DSD Audio, 64x32 kHz
0b010 DSD Audio, 64x44.1 kHz
0b011 DSD Audio, 64x48 kHz
0b100 DSD Audio, 64x88.2 kHz
0b101 DSD Audio, 64x96 kHz
0b110 DSD Audio, 64x176.4 kHz
0b111 DSD Audio, 64x192 kHz
6.11.3.4. HBR Audio
The ADV8005 uses an HBR audio packet to transmit across the TMDS link compressed audio streams conforming to IEC 61937 and with high
bit rate (that is, bit rate higher than 6.144 Mbps).
The
ADV8005 can be configured to receive an HBR stream by setting audio_input_sel[2:0] to 0b011. The use of one or four input stream(s)
with or without biphase mark (BPM) encoding can be selected via the audio_mode[1:0] field. Note that an audio master clock input through
the pin MCLK_IN is always required for the BPM encoding modes. For HBR mode, the audio sampling frequency must be set via the
audioif_sf[2:0] field.
papb_sync can be toggled from 0 to 1 to synchronize the Pa and Pb syncword, which marks the beginning of a stream repetition with the
subpacket 0. For data bursts with a repetition period, which is a multiple of four frames, the synchronization will persist. If the data burst does
not have a repetition period of four frames, setting
papb_sync is not needed but will not have any negative effects. The transition of the bit from
0 to 1 causes the one time synchronization, so setting the bit from 1 to 0 will have no effect.
The mapping between the I2S input signals to the Tx core and the HBR subpackets can be via the following controls:
•
subpkt0_l_src
•
subpkt0_r_src
•
subpkt1_l_src
•
subpkt1_r_src
•
subpkt2_l_src
•
subpkt2_r_src
•
subpkt3_l_src
•
subpkt3_r_src
Note: When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8005 , the fields listed above are
set to the respective default values. Since there is no standard for chip to chip HBR transfer, different settings may be required to map the HBR
stream input to the Tx core and a non ADI HDMI Rx device.
Refer to
Table 59 for additional details on the HBR modes supported by the ADV8005 .
papb_sync , TX2 Main Map, Address 0xF447[6]
This bit is used to synchronize the Pa and Pb syncwords with subpacket 0 for HBR audio.
Function
papb_sync Description
0 (default) No function
1 Synchronize Pa and Pb syncwords with subpacket 0
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