Analog Devices ADV8005, Справочник по аппаратуре

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UG-707 ADV8005 Hardware Reference Manual
The following standards are NOT supported.
VI
C
Format Int/Pr
og
Field
Rate
[Hz]
Pix
el
Fre
q
[MH
z]
H
Fre
q
[kH
z]
V
Fre
q
[Hz
]
H
tota
l
[dot
s]
H
acti
ve
[dot
s]
H
bla
nk
[dot
s]
H
Fro
nt
Por
ch
[dot
s]
Hsy
nc
[dot
s]
H
Bac
k
Por
ch
[dot
s]
V
total
[line
s]
V
acti
ve
[line
s]
V
blan
k
[line
s]
V
Fro
nt
Por
ch
[line
s]
Vsy
nc
[line
s]
V
Bac
k
Por
ch
[line
s]
63 1920x10
80p
Prog 119,88/
120
594 270 12
0
220
0
192
0
280 88 44 148 225
0
220
5
45 4 5 36
64
1920x10
80p
Prog 100 594 225 10
0
264
0
192
0
720 528 44 148 225
0
220
5
45 4 5 36
3.5.5. 3D Side by Side Full
The following 3D standards need to go through the HPS before being converted to a 2D mode.
VI
C
Format Int/Pr
og
Field
Rate
[Hz]
Pix
el
Fre
q
[MH
z]
H
Fre
q
[kH
z]
V
Fre
q
[Hz
]
H
tota
l
[dot
s]
H
acti
ve
[dot
s]
H
bla
nk
[dot
s]
H
Fro
nt
Por
ch
[dot
s]
Hsy
nc
[dot
s]
H
Bac
k
Por
ch
[dot
s]
V
total
[line
s]
V
acti
ve
[line
s]
V
blan
k
[line
s]
V
Fro
nt
Por
ch
[line
s]
Vsy
nc
[line
s]
V
Bac
k
Por
ch
[line
s]
63 1920x10
80p
Prog 119,88/
120
297 135 12
0
220
0
192
0
280 88 44 148 112
5
108
0
45 4 5 36
64 1920x10
80p
Prog 100 297 112
.5
10
0
264
0
192
0
720 528 44 148 112
5
108
0
45 4 5 36
3.6. EXTERNAL SYNC MODE
Using the ADV8005 external sync mode, it is possible to resynchronise multiple ADV8005 output video streams to an external sync input. The
outputs from multiple ADV8005 devices will be locked to +/- 3 Xtal clock cycles, where the Xtal clock will be 27 MHz.
When the
ADV8005 is in external sync mode, the output video timing will be locked to an externally provided master sync signal (MAS_VS).
This master signal must be provided to the MAS_VS ball. The polarity of this sync signal is assumed to be active high and will default to this
operation.
mas_vs_ie , mas_hs_ie , and mas_clk_ie are used to enable the respective external sync pins.
Assumptions for operating in this mode:
•
The external sync provided to the ADV8005 will be a CEA-861 or VESA compliant VSync. Non standard timing will NOT be
supported, that is, extra or fewer pixels, lines or frames than specified in the standard. Note that the VS and HS are assumed to be
active high.
•
The sync signals supported will be VS and HS. Note that HS is optional and only required if interlaced output is required. In this case
the HS position with respect to the VS will be used to determine the output field required. If only progressive outputs are required then
the HS may be omitted and VS alone will suffice to lock the output.
•
The external timing provided should match the output video standard programmed. For example if 1080i60Hz is to be output from
the
ADV8005 PVSP and locked to external timing then a 60 Hz Vsync signal should be provided on the MAS_VS pin and a
33.750 kHz HSync should be provided on the MAS_HS pin. In this case the pvsp_autocfg_output_vid[7:0] should be set to 5.
Rev. A | Page 162 of 317