ADV8005 Hardware Reference Manual
UG-707
dis_cable_det_rst
, HDMI RX Map,
Address 0xE248[6]
This bit is used to disable the reset effects of cable detection. It should be set to 1 if the +5 V pins are unused and left unconnected.
Function
dis_cable_det_rst
Description
0 (default)
Resets the HDMI section if the 5 V input pin is inactive
1
Do not use the 5 V input pins as reset signal for the HDMI section
5.2.
TMDS CLOCK ACTIVITY DETECTION
The
Serial Video Rx provides circuitry to monitor TMDS clock activity and also the type of data on the Rx input lines. System software
can poll these registers and configure the
and
can be used to determine if there is
a valid clock on the TMDS clock input and if the Serial Video Rx has locked to this. If both of these are true,
can be used to
indicate the video data that is available on the Serial Video Rx, either DVI data or HDMI data.
rx_hdmi_mode
, HDMI RX Map,
Address 0xE205[7] (Read Only)
This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream.
Function
rx_hdmi_mode
Description
0 (default)
DVI Mode Detected
1
HDMI Mode Detected
rb_rx_tmds_clk_det
, IO Map,
Address 0x1ADF[3] (Read Only)
This bit is used to indicate if there is a clock on the Serial Video RX input lines.
Function
rb_rx_tmds_clk_det
Description
0 (default)
No TMDS clock detected on the Serial Video RX input lines
1
TMDS clock detected on Serial Video RX input lines
tmds_pll_locked
, HDMI RX Map,
Address 0xE204[1] (Read Only)
This bit is a readback to indicate if the TMDS PLL is locked to the TMDS clock input of the selected HDMI port.
Function
tmds_pll_locked
Description
0 (default)
The TMDS PLL is not locked
1
The TMDS PLL is locked to the TMDS clock input of the selected HDMI port.
Note:
The tmds_pll_locked flag should be considered valid if a TMDS clock is input on the Serial Video Rx.
freqtolerance[3:0]
, HDMI RX Map,
Address 0xE20D[3:0]
Sets the tolerance in MHz for new TMDS frequency detection. This tolerance is used for the audio mute mask mt_msk_vclk_chng and the
HDMI status bit new_tmds_frq_raw.
Function
freqtolerance[3:0]
Description
0100
Default tolerance in MHz for new TMDS frequency detection
xxxx
Tolerance in MHz for new TMDS frequency detection
5.3.
CLOCK AND DATA TERMINATION CONTROL
The
provides the
control for TMDS clock and data termination on all Serial Video Rx input pins.
clock_terma_disable
, HDMI RX Map,
Address 0xE283[0]
This control is used to disable clock termination on port A. It can be used when term_auto is set to 0.
Function
clock_terma_disable
Description
0
Enable Termination port A
1 (default)
Disable Termination port A
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