ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 127 of 196
SPI WIRE-OR’ED MODE (WOM)
To prevent contention when the SPI is used in a multimaster or multislave system, the data output pins, MOSI and MISO, can be
configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected. The WOM bit
(SPIxCON[4]) controls the pad enable outputs for the data lines.
SPI CSERR CONDITION
The CSERR bit (SPIxSTA[12]) indicates if an erroneous deassertion of the CS signal has been detected before the completion of all eight
SCLK cycles. This bit generates an interrupt and is available in all modes of operation: slave, master, and during DMA transfers.
If an interrupt generated by the CSERR bit (SPIxSTA[12]) occurs, the SPI ENABLE bit (SPIxCON[0]) should be disabled and restarted to
enable a clean recovery. This ensures that subsequent transfers are error free. The BCRST bit (SPIxDIV[7]) should be set at all times in
both slave mode and master mode except when a midbyte stall in SPI communication is required. In this case, the CSERR flag is set but
can be ignored.
TRANSMIT
DATA
CS
SPIxDIV[7]
BCRST = 0
DATA 0
8 BITS
5 BITS
DATA 1
3 BITS
DATA 1
DATA 2
8 BITS
IGNORE CSERR (SPIxSTA[12])
1
117
6-
027
Figure 24. SPI Communication: Midbyte Stall
Note that the SPI should only be reenabled when the CS signal is high.
SPI DMA
DMA operation is provided on both SPI channels. Two DMA channels are dedicated to transmit and receive. The SPI DMA channels
should be configured in the μDMA controller of the ARM Cortex-M3 processor.
It is possible to enable a DMA request on one or two channels at the same time by setting the DMA request bits for receive or transmit in
the SPIxDMA register. If only the DMA transmit request (SPIxDMA[1]) is enabled, the Rx FIFO overflows during an SPI transfer, unless
the received data is read by user code, and an overflow interrupt is generated. To avoid generating overflow interrupts, the Rx FIFO flush
bit should be set or the SPI interrupt should be disabled in the NVIC. If only the DMA receive request (SPIxDMA[2]) is enabled, the Tx
FIFO is underrun. To avoid an underrun interrupt, the SPI interrupt should be disabled.
The SPI Tx (SPIxSTA[5]) and SPI Rx (SPIxSTA[6]) interrupts are not generated when using DMA. The SPI TXUR (SPIxSTA[4]) and
RXOF (SPIxSTA[7]) interrupts are generated when using DMA. The SPIxCON[15:14] bits are not used in transmit mode and should be
set to 0x00 in receive mode.
The enable bit (SPIxDMA[0]) controls the start of a DMA transfer. DMA requests are only generated when enable = 1. At the end of a
DMA transfer, that is, when receiving a DMA SPI transfer interrupt, this bit needs to be cleared to prevent extra DMA requests to the
μDMA controller. The data still present in the Tx FIFO is transmitted if in Tx mode.
DMA Master Transmit Configuration
The DMA SPI Tx channel should be configured.
The NVIC should be configured to enable DMA Tx master interrupt (for example, enable DMA Tx master interrupt SPI0 Tx using ISER0[26]).
When all data present in the DMA buffer are transmitted, the DMA generates an interrupt. User code should disable the DMA request.
Data is still in the Tx FIFO because the DMA request is generated each time there is free space in the Tx FIFO to always keep the FIFO
full. User code can check how many bytes are still present in the FIFO in the FIFO status register.
DMA Master Receive Configuration
The SPIxCNT register is available in DMA receive master mode only. It sets the number of receive bytes required by the SPI master or the
number of clocks that the master needs to generate. When the required number of bytes are received, no more transfers are initiated. To initiate a
DMA master receive transfer, a dummy read should be completed by user code. This dummy read should be added to the SPIxCNT number.
The counter counting the bytes as they are received is reset either when SPI is disabled in SPIxCON[0] or if the SPIxCNT register is modified
by user code.
