UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 12 of 196
CLOCKING ARCHITECTURE OVERVIEW
The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0
can also be used for test purposes.
Internally, the system clock is divided into separate clocks:
•
UCLK system clock
•
HCLK for the flash, SRAM, and DMA
•
PCLK for most peripherals
•
ACLK for the analog section of the chip; this is based on PCLK output and goes to the low voltage analog die
All ADC performance details are based on a 20 MHz ACLK (CLKCON1[10:8] = 0b010). Performance at other clock speeds is not
guaranteed; therefore, CLKCON1[10:8] should not be changed when the ADC is being used.
REGISTER SUMMARY: CLOCK ARCHITECTURE
Table 4. Clocking Register Summary
Address
Name
Description
Reset
RW
0x40028000
CLKCON0
Misc clock settings register
0x0041
RW
0x40028004
CLKCON1
Clock dividers register
0x0200
RW
0x40028014
CLKCON5
User clock gating control register
0x0040
RW
0x40028018
CLKSTAT0
Clocking status
0x0000
RW
CLOCKING ARCHITECTURE OPERATION
At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the
internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1
to 128, where the clock divider bits are controlled by CLKCON1[2:0]. Slower code execution and reduced power consumption result.
Note that P1.0 must be configured as a clock input before the clock source is switched in the clock control register.
When changing from one clock source to a different clock source, the user code must ensure that both clock sources are kept active for a
minimum of five clock cycles to ensure that the clock switching is fully completed without any glitches.
If the clock source for the 80 MHz SPLL needs to be changed from the internal 16 MHz oscillator to the external HFXTAL, observe the
following procedure:
1.
Check that HFXTAL is stable by reading CLKSTAT0[14:12].
2.
Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0].
3.
Wait 5 × 16 MHz clock cycles.
4.
Switch the input to the SPLL using CLKCON0[11].
5.
Wait until the SPLL has locked by monitoring CLKSTAT0[2:0].
6.
Change the system clock back to the SPLL clock.
