ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 25 of 196
To calculate the die temperature, use the following formula:
T
−
T
REF
= (
V
ADC
−
V
TREF
) ×
K
where:
T
is the temperature result.
T
REF
is 25°C.
V
ADC
is the average ADC result from two consecutive conversions.
V
TREF
is the ADC result in millivolts that corresponds to T
REF
= 25°C. The user must measure this in their own application because this
value varies from device to device. The typical value used for demonstration purposes is 1290 mV.
K
is the gain of the ADC in temperature sensor mode. The user should determine the gain by performing a two-point temperature
calibration because this value varies from device to device. The typical value used for demonstration purposes only is 4.394 mV/°C.
This corresponds to 1/V TC.
Using the default values from the
data sheet without any calibration, the equation becomes
T
− 25°C = (
V
ADC
− 1290) × 1/
K
.
Therefore, assuming
V
ADC
at 25°C = 1290 mV and slope mV/C = 4.394 mV/C,
T
= ((
V
ADC
− 1290)/4.394) + 25
where:
V
ADC
is in millivolts.
Check the latest version of the
data sheet for the most up to date figures.
For increased accuracy, perform a two-point calibration at a controlled temperature value.
The values used in this example for V
TREF
and K are not guaranteed values. The values V
TREF
and K varies from device to device; therefore,
the user must derive the appropriate values by performing a calibration at ambient temperature.
AVDD/2 and IOVDD/2 Supply Voltage Channels
These supply voltage channels are measured via internal resistor dividers. Because the resistors used are high impedance and the divided
voltage is not buffered, a slower ADC update rate should be used.
The ADC automatically changes the ADC update rate to 80 kSPS when the temperature sensor, AVDD/2, or IOVDD/2 input channel is
selected. If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed,
the ADCCNVC register must be updated.
Note that when the sequencer is enabled and includes any of these three channels, the value in the ADCCNVC register does not change
and the ADC sampling rate does not change. At rates above 80 kSPS, the accuracy is reduced if the input buffer is disabled.
ADC SUPPORT CIRCUITS
IDAC Channels
The
allows the voltage on the IDAC output pins to be selected as inputs to the ADC. These channels are useful for
determining the power consumed by each IDAC.
ADC Digital Comparator
A digital comparator is provided to allow an interrupt to be triggered if the ADC data result is above or below a programmable threshold.
Only the AIN4 external input channel can be used with the digital comparator.
To set up the ADC digital comparator, note the following:
•
ADCCMP[17:2] are used to set a 16-bit ADC threshold value.
•
ADCCMP[1] configures the comparator to be triggered when the ADC result is above or below the threshold value.
•
To enable the ADC comparator interrupt, set INTSEL[2] = 1 to enable the digital comparator to the Low Voltage Die Interrupt 1 signal.
•
Similarly, set INTSEL[10] = 1 to enable the digital comparator interrupt to the Low Voltage Die Interrupt 0 signal.
•
The comparator output is asserted when the value in ADCDAT4[27:12] rises above the value in ADCCMP[17:2] if ADCCMP[1] = 1.
If ADCDAT4[27:12] remains above ADCCMP[17:2], no further comparator interrupts occur. The interrupt only occurs when the
comparator circuit detects a rise above the threshold.
•
Similarly, if ADCCMP[1] = 0, the comparator output is asserted when the value in ADCDAT4[27:12] falls below the value in
ADCCMP[17:2]. If ADCDAT4[27:12] remains below ADCCMP[17:2], no further comparator interrupts occur. The interrupt only
occurs when the comparator circuit detects a fall below the threshold value.
