ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 79 of 196
FEEPRO0 and FEEPRO1 at startup, with each bit protecting a block of 4 kB of flash. If no protection is specified, protection can be set by
writing to FEEPRO0 and FEEPRO1.
Flash Failure Analysis Key
It may be necessary to perform failure analysis on parts that are returned by a user even though read protection is enabled. A method has
been provided to allow failure analysis of protected memory by a user flash failure analysis key (USERFAAKEY.).
The user must set the key as two 32-bit values near the top of each user flash block. Supplying this key to Analog Devices allows access to
user code for debug purposes. See Figure 14 and Figure 15 for details.
Flash Controller Abort
Commands (erase, sign, or mass verify) and writes can be aborted upon receipt of an interrupt, as listed in Table 54. Aborts are also
possible by writing an abort command to the FEECMD register. However, if flash is being programmed and the routine controlling the
programming is in flash, it is not possible to use the abort command to abort the cycle because instructions cannot be read. Therefore, the
ability to abort a cycle on the assertion of any system interrupt is provided. The FEEAENx register is used to enable aborts upon receipt of
an interrupt. Each bit in the FEEAENx registers corresponds to an interrupt listed in Table 54. Setting a bit in the FEEAENx register
enables the corresponding interrupt to abort flash operations.
When a command or write is aborted via a system interrupt, FEESTA[5:4] indicates an abort (FEESTA[5:4] = 11).
Depending on the state that a write cycle is in when the abort asserts, the write cycle may or may not complete. If the write or erase cycle
did not complete successfully, a fail status of aborted can be read in the status register.
If an immediate response to an interrupt is required during an erase or program cycle, the interrupt service routine and the interrupt
vector table must be moved to SRAM or must be in the other flash block for the duration of the cycle.
If the DMA engine is set up to write a block of data to flash, an interrupt can be set up to abort the current write; however, the DMA
engine starts the next write immediately. The interrupt causing the abort stays asserted so that there is a number of aborted write cycles
in this case before the processor gains access to flash.
When an abort is triggered by an interrupt, all commands are repeatedly aborted until the appropriate FEEAENx bit is cleared or the
interrupt source is cleared.
CPU Execution Speed
The basic execution speed of the
is one CPU cycle per clock cycle. The default clock speed is 80 MHz, which is achieved
when running from cache, but is slightly less when running directly from flash. An average execution speed of over 70 MHz is typically
achieved for typical C code. For more details and how to achieve full speed operation for critical code, see the
Memory Cache
A memory cache is provided on chip to speed up program execution. The instruction cache is configured and set up by default. If the
user writes code to the flash, the user should perform a chip reset to ensure that the old cached data is cleared and that the new code
can be executed. If a chip reset is not possible, the following code can be used to clear the cache. iCache should be 0x10001 or
(CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN) to clear both the instruction and data cache.
int FeeCacheClr(int iCache)
{
unsigned int ui1;
ui1 = pADI_FEE->CACHESETUP;
pADI_FEE->CACHEKEY = 0xF123F456;
pADI_FEE->CACHESETUP = ui1|(iCache&(CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN));
while(pADI_FEE->CACHESTAT&(iCache&(CACHESETUP_IINIT_EN|CACHESETUP_DINIT_EN)));
pADI_FEE->CACHEKEY = 0xF123F456;
pADI_FEE->CACHESETUP = ui1;
return 1;
}
Most programming tools clear the cache before downloading code to a device.
