Analog Devices ADuCM320, Справочник по аппаратуре

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ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 119 of 196
Slave I 2 C Status/Error/IRQ Register
Address: 0x4000342C, Reset: 0x0001, Name: I2C1SSTA
Table 167. Bit Descriptions for I2C1SSTA
Bits Bit Name Description Reset Access
15 RESERVED Reserved. 0x0 R
14 START Start and matching address. This bit is asserted if a start is detected on
SCL/SDA and the device address matched, or a general call (GC) (address =
0000_0000) code is received and GC is enabled, or a high speed (address =
0000_1XXX) code is received, or a start byte (0000_0001) is received. It is
cleared on receipt of either a stop or start condition.
0x0 R
13 REPSTART Repeated start and matching address. This bit is asserted if START is
already asserted and then a repeated start is detected. It is cleared when
read or on receipt of a STOP condition. This bit can drive an interrupt.
0x0 RC
[12:11] IDMAT Device ID matched. 0x0 R
00: received address matched ID register 0
01: received address matched ID register 1
10: received address matched ID register 2
11: received address matched ID register 3
10 STOP Stop after start and matching address. Gets set by hardware if the slave
device received a STOP condition after a previous START condition and a
matching address. Cleared by a read of the status register. If STOPINTEN in
the slave control register is asserted, the slave interrupt request asserts
when this bit is set. This bit can drive an interrupt.
0x0 RC
[9:8] GCID General ID. GCID is cleared when the GCSBCLR is written to 1. These status
bits are not cleared by a general call reset. 0x0 R
00: no general call
01: general call reset and program address
10: general call program address
11: general call matching alternative ID
7 GCINT General call interrupt. This bit always drives an interrupt. The bit is asserted
if the slave device receives a general call of any type. To clear, write 1 to the
GCSBCLR in the slave control register. If it was a general call reset, all
registers are at their default values. If it was a hardware general call, the Rx
FIFO holds the second byte of the general call, and this can be compared
with the ALT register.
0x0 R
6 SBUSY Slave busy. Set by hardware if the slave device receives a I
2
C START
condition. Cleared by hardware when the address does not match an ID
register, the slave device receives a I
2 C STOP condition, or if a repeated
start address does not match.
0x0 R
5 NOACK ACK not generated by the slave. When asserted, it indicates that the slave
responded to its device address with a NOACK. It is asserted if there was
no data to transmit and sequence was a slave read or if the NACK bit was
set in the slave control register and the device was addressed. This bit is
cleared on a read of the I2CSSTA register.
0x0 RC
4 SRXOF Slave receive FIFO overflow. Asserts when a byte is written to the slave
receive FIFO when the FIFO is already full. 0x0 RC
3 SRXREQ Slave receive request. SRXREQ asserts whenever the slave receive FIFO is
not empty. Read or flush the slave receive FIFO to clear this bit. This bit
asserts on the falling edge of the SCL clock pulse that clocks in the last
data bit of a byte. This bit can drive an interrupt.
0x0 RC