UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 66 of 196
Peripheral Scatter-Gather (CHNL_CFG[2:0] = 110 or 111)
In peripheral scatter-gather mode, the controller must be configured to use both the primary and alternate data structure. The controller
uses the primary data structure to program the control structure of the alternate data structure. The alternate data structure is used for
actual data transfers, and each transfer takes place using the alternate data structure with a basic DMA transfer. The controller does not
arbitrate after every primary transfer. This mode is used when there are multiple peripheral-to-memory DMA tasks to be performed. The
Cortex-M3 can configure all of the tasks simultaneously and does not need to intervene in between each task. This is very similar to
memory scatter-gather mode except for arbitration and request requirements. The controller generates the corresponding DMA channel
interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle.
In peripheral scatter-gather mode, the controller receives an initial request from a peripheral and then performs four DMA transfers
using the primary data structure to program the alternate control data structure. The controller then immediately starts a DMA cycle
using the alternate data structure without rearbitrating.
After this cycle completes, the controller rearbitrates, and if it receives a request from the peripheral that has the highest priority, it
performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data
structure without rearbitrating. The controller continues to alternate between using the primary and alternate data structures until either
the processor configures the alternate data structure for a basic cycle or the DMA reads an invalid data structure.
Table 76 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant
values for the peripheral scatter-gather mode.
Table 76. CHNL_CFG for Primary Data Structure in Peripheral Scatter-Gather Mode, CHNL_CFG[2:0] = 110
Bits Name
Description
[31:30]
DST_INC
10: configures the controller to use word increments for the address.
[29:28]
DST_SIZE
10: configures the controller to use word transfers.
[27:26]
SRC_INC
10: configures the controller to use word increments for the address.
[25:24]
SRC_SIZE
10: configures the controller to use word transfers.
[23:18]
RESERVED
Undefined. Write as 0.
[17:14]
R_POWER
0010: indicates that the DMA controller performed four transfers without rearbitration.
[13: 4]
N_MINUS_1
Configures the controller to perform N DMA transfers, where N is a multiple of 4.
3
RESERVED
Undefined. Write as 0.
[2:0]
CYCLE_CTRL
110: configures the controller to perform a memory scatter-gather DMA cycle.
ADDRESS CALCULATION
The DMA controller calculates the source read address based on the content of SRC_END_PTR, the source address increment setting in
CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]).
Similarly, the destination write address is calculated based on the content of DST_END_PTR, the destination address increment setting in
CHNL_CFG, and the current value of N_MINUS_1 (CHNL_CFG[13:4]).
Source Read Address = SRC_END_PTR
−
(N_MINUS_1 << (SRC_INC)) for SRC_INC = 0, 1, 2
Source Read Address = SRC_END_PTR for SRC_INC = 3
Destination Write Address = DST_END_PTR
−
(N_MINUS_1 << (DST_INC)) for DST_INC = 0, 1, 2
Destination Write Address = DST_END_PTR for DST_INC = 3
where
N_MINUS_1
is the number of configured transfers minus 1 for that channel.
ABORTING DMA TRANSFERS
It is possible to abort a DMA transfer that is in progress by writing to the bit in the DMAENCLR register corresponding to the channel
that needs to be aborted. Do not set DMACFG = 0 because this can corrupt the DMA structures.
