UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 126 of 196
SPI INTERRUPTS
There is one interrupt line per SPI and four sources of interrupts. SPIxSTA[0] reflects the state of the interrupt line, and SPIxSTA[7:4]
reflects the state of the four sources.
The SPI generates either TIRQ or RIRQ. Both interrupts cannot be enabled at the same time. The appropriate interrupt is enabled using
the TIM bit, SPIxCON[6]. If TIM = 1, TIRQ is enabled. If TIM = 0, RIRQ is enabled.
In addition, note that the SPI0 and SPI1 interrupt source must be enabled in the NVIC register as follows: ISER0[19] = SPI0, ISER0[20] = SPI1.
Tx Interrupt
If TIM (SPIxCON[6]) is set, the Tx FIFO status causes the interrupt. The SPIxCON[15:14] bits control when the interrupt occurs, as
shown in Table 177.
Table 177. SPIxCON[15:14] IRQ Mode Bits
SPIxCON[15:14] Interrupt Condition
00
An interrupt is generated after each byte that is transmitted. The interrupt occurs when the byte is read from the FIFO
and written to the shift register.
01
An interrupt is generated after every two bytes that are transmitted.
10
An interrupt occurs after every third byte that is transmitted.
11
An interrupt occurs after every fourth byte that is transmitted.
The interrupts are generated depending on the number of bytes transmitted and not on the number of bytes in the FIFO. This is unlike
the Rx interrupt, which depends on the number of bytes in the Rx FIFO and not the number of bytes received.
The transmit interrupt is cleared by a read to the status register. The status of this interrupt can be read by reading SPIxSTA[5]. The
interrupt is disabled if SPIxCON[13] is left high.
A write to the control register, SPIxCON, resets the transmitted byte counter back to 0. For example, in a case where SPIxCON[15:14] is
set to 0x3 and SPIxCON is written to after three bytes have been transmitted, the Tx interrupt does not occur until another four bytes
have been transmitted.
Rx Interrupt
If TIM (SPIxCON[6]) is cleared, the Rx FIFO status causes the interrupt. The SPIxCON[15:14] bits control when the interrupt occurs.
The interrupt is cleared by a read of SPIxSTA. The status of this interrupt can be read by reading SPIxSTA[6].
Interrupts are only generated when data is written to the FIFO. For example, if the SPIxCON[15:14] bits are set to 0x00, an interrupt is
generated after the first byte is received. When the status register is read, the interrupt is deactivated. If the byte is not read from the FIFO,
the interrupt is not regenerated. Another interrupt is not generated until another byte is received in the FIFO.
The interrupt depends on the number of valid bytes in FIFO and not the number of bytes received. For example, when the SPIxCON[15:14] bits
are set to 0x1, an interrupt is generated after a byte is received if there are two or more bytes in the FIFO. The interrupt is not generated
after every two bytes received.
The interrupt is disabled if SPIxCON[12] is left high.
Underrun/Overflow Interrupts
SPIxSTA[7] and SPIxSTA[4] generate SPI interrupts.
When a transfer starts with no data in the Tx FIFO, SPIxSTA[4] is set to indicate an underrun condition. This causes an interrupt. The
interrupt (and status bit) are cleared upon a read of the status register. This interrupt occurs irrespective of SPIxCON[15:14]. This
interrupt is disabled if SPIxCON[13] is set.
When data is received and the Rx FIFO is already full, SPIxSTA[7] is set to 1, indicating an overflow condition. This causes an interrupt.
The interrupt (and status bit) are cleared upon a read of the status register. This interrupt occurs irrespective of SPIxCON[15:14]. This
interrupt is disabled if SPIxCON[12] is set.
When the SPI Rx overflow bit (SPIxSTA[7]) is set to 1, the contents of the SPI Rx FIFO are undetermined and should not be used. The
user should flush the Rx FIFO upon detecting this error condition.
All interrupts are cleared either by a read of the status register or when SPIxCON[0] is deasserted. The Rx and Tx interrupts are also
cleared if the relevant flush bits are asserted. Otherwise, the interrupts stay active even if the SPI is reconfigured.
