UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 78 of 196
ECC Error Handling
During the signature check, the error checking and correcting (ECC) is checked on each 72-bit flash read (64-bit flash read and 8-bit
ECC). If errors are corrected by the ECC, the ERRDETECTED flag in the status register, FEESTA, is set after the signature check is
completed. If errors are detected and cannot be corrected by ECC, the ERRDETECTED flag in FEESTA is set. A signature check is treated
as a failure when the computed signature is not equal to the stored signature.
During a read of the flash, if there is a 1-bit error, the error is corrected by default; however, neither ECC interrupts nor system exceptions
are enabled. If interrupts or system exceptions are not enabled by the user, the appropriate flags in FEESTA are not set in the event of an
ECC error.
A 1-bit ECC interrupt or system exception can be enabled in the ECC enable/disable register (FEEECCCONFIG), if required. If the
appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in the status
register.
If there is a 2-bit ECC error and if interrupts or system exceptions are enabled in the FEEECCCONFIG register, an error is issued by the
controller. If the appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in
the status register.
An ECC error is signaled by the ECC error detection/correction hardware when a flash location is read. Depending on from which flash
(Flash 0 or Flash 1) the read happens, the appropriate flags are set in the status register (ECCREADERRFLSH0, ECCREADERRFLSH1,
and so on). Note that 1-bit errors corrected meet full data sheet specification.
If a system exception is enabled, the device vectors to a hard fault or bus fault in the event of an ECC error. See the SHCSR register in the
ARM Cortex-M3 processor documentation to enable a bus fault.
ECC Error During Read
Two separate ECCREADERR flags are present in the status register: FEESTA[10:9] and FEESTA[12:11] for Flash 0 And Flash 1. If the
interrupt is configured to be generated when an ECC error occurs, the address at which the error is detected is available for the user. If a
system exception is configured, the BFAR register contains the address for which ECC error is detected.
ECC Error During Execution of Sign Command
If there is an ECC error during signature check, registers are not updated. After the command is complete, ECCERRCMD flags in
FEESTA[8:7] are updated. No interrupt or system exception is generated.
FLASH PROTECTION
There are three types of protection implemented:
•
Key protection
•
Read protection
•
Write protection
Flash Protection: Key Protection
Some of the flash controller MMRs are key-protected to avoid accidental writes to these MMRs.
The user key is 0xF123F456. This key must be entered to run certain user commands, to write to certain locations in flash, or to enable
write access to FEECON1. Once entered, the key remains asserted unless a command is written to FEECMD. When the command starts,
the key clears automatically. If this key is entered to enable write access to FEECON1 or to enable writes to certain locations in flash, it
needs to be cleared by user code afterwards. To clear the key, write any value other than 0xF123F456 to FEEKEY.
Flash Protection: User Read Protection
User space read protection is provided by disabling serial wire access. A user can disable serial wire debug access by writing 0 to Bit 0 of
FEECON1. Serial wire debug access is disabled while the kernel is running; otherwise, serial wire debug access may prevent the kernel
from running to completion. When the kernel exits to user code, it enables serial wire access unless either of the keys at 0x3FFF4 or
0x1FFF4 is set to 0x0000003A. This means that the part is always read protected after either key is in place and that no debug access can occur.
Flash Protection: User Write Protection
User write protection is provided to prevent accidental writes to pages in user space and to protect blocks of user code when downloading
extra code to flash. If a write or erase of a protected location is detected, the flash controller generates an interrupt if the command
error/complete interrupt are enabled. The write protection for each block is stored near the top of each block. The top four bytes are for a
signature, and the next eight bytes are reserved. The next 32-bit flash location contains the protection pattern, which is copied to
