Analog Devices ADuCM320, Справочник по аппаратуре

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ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 89 of 196
Cache Status Register
Address: 0x400180C0, Reset: 0x00000002, Name: CACHESTAT
Table 115. Bit Descriptions for CACHESTAT
Bits Bit Name Description Reset Access
[31:20] RESERVED Reserved. 0x0 R
18 DLOCK This bit is set when D-Cache is locked and cleared when D-Cache is unlocked. 0x0 R
17 DEN If this bit is set then D-Cache is enabled and when cleared D-Cache is disabled. This is
also cleared when CACHESTAT[16] is set. 0x0 R
16 DINIT It is set when D-cache memory initialization starts and clears when initialization is
done. D-Cache is disabled when this bit is set. 0x0 R
[15:4] RESERVED Reserved. 0x0 R
2 ILOCK This bit is set when I-Cache is locked and cleared when I-cache is unlocked. 0x0 R
1 IEN If this bit is set then I-Cache is enabled and when cleared I-Cache is disabled. This is
also cleared when CACHESTAT[0] is set. 0x1 R
0 IINIT It is set when I-cache memory initialization starts and clears when initialization is
done. I-Cache is disabled when this bit is set. 0x0 R
Cache Setup Register
Address: 0x400180C4, Reset: 0x00000002, Name: CACHESETUP
This register is key-protected; therefore, the key (0xF123F456) must be entered in CACHEKEY.
Table 116. Bit Descriptions for CACHESETUP
Bits Bit Name Description Reset Access
[31:20] RESERVED Reserved. 0x0 RW
19 DWRBUF If this bit is set, for every AHB access, hit from write buffer is not checked. 0x0 RW
18 DLOCK If this bit is set, D-cache contents are locked. Any new misses are not replaced in
D-Cache. This bit is cleared when CACHESETUP[16] is set. 0x0 RW
17 DEN If this bit set, D-Cache is enabled for AHB accesses. If 0, D-cache is disabled, and all
AHB accesses are via Flash memory. This bit is cleared when CACHESETUP[16] is set. 0x0 RW
16 DINIT If this bit is set, the D-cache contents are initialized to all zeros. This bit is cleared
when the initialization starts. 0x0 RW
[15:5] RESERVED Reserved. 0x0 RW
4 IRDBUF If this bit is set, for every AHB access, hit from read buffer is not checked. 0x0 RW
3 IWRBUF If this bit is set, for every AHB access, hit from write buffer is not checked. 0x0 RW
2 ILOCK If this bit is set, I-cache contents are locked. Any new misses are not replaced in
I-Cache. This bit is cleared when CACHESETUP[0] is set. 0x0 RW
1 IEN If this bit set, I-Cache is enabled for AHB accesses. If 0, then I-cache is disabled, and
all AHB accesses are via Flash memory. This bit is cleared when CACHESETUP[0] is set. 0x1 RW
0 IINIT If this bit is set, the I-cache contents are initialized to all zeros. This bit is cleared
when the initialization starts. 0x0 RW
Cache Key Register
Address: 0x400180C8, Reset: 0x00000000, Name: CACHEKEY
Table 117. Bit Descriptions for CACHEKEY
Bits Bit Name Description Reset Access
[31:0] KEY Cache key register. Enter 0xF123F456 to allow key protected operations. Returns 0x0
if read. The key is cleared automatically after writing to the setup register. 0x0 W