ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 137 of 196
UART SERIAL INTERFACE
UART FEATURES
•
Industry-standard 16,450 UART peripheral
•
Support for DMA
UART OVERVIEW
The UART peripheral is a full-duplex universal asynchronous receiver/transmitter (UART), compatible with the industry-standard
16,450. The UART is responsible for converting data between serial and parallel formats. The serial communication follows an
asynchronous protocol, supporting various word lengths, stop bits, and parity generation options.
This UART also contains interrupt handling hardware. The UART features a fractional divider that facilitates high accuracy baud rate
generation.
Interrupts can be generated from several unique events, such as full/empty data buffer, transfer error detection, and break detection.
UART OPERATION
Serial Communications
An asynchronous serial communication protocol is followed with these options:
•
5 to 8 data bits
•
1, 2, or 1½ stop bits
•
None, even, or odd parity
•
The baud rate is as follows:
Baud Rate
=
UCLK
/
CDPCLK
÷ (2 × 16 ×
COMDIV
) ÷ (
M
+
N
÷ 2048)
where:
COMDIV
= 1 to 65,536.
M
= 1 to 3.
N
= 0 to 2047.
UCLK
/
CDPCLK
is the divided 80 MHz clock as configured via CLKCON1[10:8]
All data-words require a start bit and at least one stop bit. This creates a range from seven bits to twelve bits for each word. Transmit
operation is initiated by writing to the transmit holding register (COMTX). After a synchronization delay, the data is moved to the
internal transmit shift register (TSR), where it is shifted out at a baud (bit) rate equal to the following with start, stop, and parity bits
appended as required:
UCLK
/
CDPCLK
÷ (2 × 16 ×
COMDIV
) ÷ (
M
+
N
÷ 2048)
All data-words begin with a low-going start bit. The transfer of COMTX to the TSR causes the transmit register empty status flag to be set.
The receive operation uses the same data format as the transmit configuration except for the number of stop bits, which is always one.
After detection of the start bit, the received word is shifted into the internal receive shift register (RSR). After the appropriate number of
bits (including stop bits) are received, the data and any status are updated, and the RSR is transferred to the receive buffer register (COMRX). The
receive buffer register full status flag is updated upon the transfer of the received word to this buffer and the appropriate synchronization delay.
A sampling clock equal to 16 times the baud rate is used to sample the data as close to the midpoint of the bit as possible. A receive filter is
also present that removes spurious pulses of less than two times the sampling clock period.
Note that data is transmitted and received least significant bit first. This is often not the assumed case by the user. However, it is standard
for the protocol.
For power saving purposes, it is possible to disable the system clock to the UART via the CLKCON5[5] register. By default, the clock to
the UART is disabled (CLKCON5[5] = 1).
Programmed I/O Mode
In this mode, the software is responsible for moving data to and from the UART. This is typically accomplished by interrupt service
routines that respond to the transmit and receive interrupts by either reading or writing data as appropriate. This mode puts certain
constraints on the software itself in that the software must respond within a certain time to prevent overflow errors from occurring in the
receive channel.
