UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 26 of 196
ADC Channel Sequencer
An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer
allows a user to select the number and order of ADC input channels that the ADC samples and provides a single interrupt source that is
asserted when the sequence ends. The sequencer can also be programmed to restart automatically without a delay or with a programmable
delay between the end and start of sequences.
Some additional details about the sequencer include the following:
•
The sequencer reads the ADCSEQ[0:27] register to determine which channels need to be included and which need to be excluded
from the execution sequence.
•
ADCSEQ corresponds to the ADCCHA[4:0] for the list of ADC input channels. For example, to include AIN9, set ADCSEQ[9].
•
To enable the sequencer as the Low Voltage Die Interrupt 1 source, set INTSEL[1] = 1. To enable the sequencer as the Low Voltage
Die Interrupt 0 source, set INTSEL[9] = 1.
•
To start the sequencer, set ADCSEQ[31:30] = 0x3.
•
The ADCSEQC[27:20] register bits are used to set the delay between finishing one sequence of channels and starting another sequence.
•
Normally, single-ended measurements are assumed by the ADC with AGND as the negative reference. However, for Channel 0,
Channel 2, Channel 4, and Channel 6, a differential measurement can be selected by configuring the appropriate bits in
ADCSEQC[19:0]. For example, ADCSEQC[4:0] selects the negative input when AIN0 is the positive. For single-ended
measurements using the sequencer and AIN0, ADCSEQC[4:0] should be set to 0x11 for VREFN_NADC (ADC_REFN pin).
•
Care should be taken when using the sequencer if the input buffer is enabled. The IBUFCON register controls the input buffer. If the
input buffer is enabled, all channels sampled in a sequence will be sampled with the input buffer enabled. It is recommended to split
sequences into the following:
o
Sample unbuffered channels together in one sequence.
o
Sample buffered channels in a separate sequence.
o
If full accuracy results are required for the AVDD/2, IOVDD/2, or temperature channels, then care must be taken when
measured with the sequencer.
With the input buffer disabled, the acquisition time should be set to 1.5 µs via ADCCONV[25:16] = 0x1E.
Or, alternatively, enable the input buffer.
ADC DMA (Direct Memory Access)
The ADC or the ADC sequencer can be selected as the source channel for the DMA controller. This reduces processor overhead by
moving ADC results directly into SRAM with a single interrupt asserted when the required number of ADC conversions has been
completely logged to memory.
When using the ADC sequencer with the DMA controller, it is recommended to use DMA autorequest transfer types rather than basic
transfer types.
ADC Voltage Reference Selection
The
integrates a low drift, 2.51 V ADC reference source. By default, this internal reference is enabled and selected as the
reference source for the ADC. When using the internal 2.51 V voltage reference, ensure the following:
•
ADCCON[7] = 1 to power up the internal reference buffer
•
AFEREFC[3] = 0 to select the internal reference as the ADC reference source
It is also possible to select an external reference source through the ADC_REFP pin.
To select an external voltage source as the ADC reference source, ensure the following:
•
ADCCON[7] = 0 to power down the internal reference buffer
•
AFEREFC[3] = 1 to select the external reference as the ADC reference source
The external reference source must be capable of driving the 4.7 µF capacitor on the ADC_REFP pin.
If switching from the external to internal reference voltage source, note that there is a power-on time specification given in the
data
sheet for the ADC reference buffer to fully power up after ADCCON[7] is set to 1.
Figure 8 shows the block diagram of how the analog references are provided.
