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ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 185 of 196
Table 288. Frame Details for Different Frame Types
1
Frame Idle
Management Frame Fields
Idle PRE ST OP PHYADR DEVADD TA Address/Data
Write Address Z 1…1 00 00 aaaaa aaaaa 10 aaaaaaaaaaaaaaaa Z
Write Data Z 1…1 00 01 aaaaa aaaaa 10 dddddddddddddddd Z
Read Data Z 1…1 00 11 aaaaa aaaaa z0 dddddddddddddddd Z
Post Read Increment Address Z 1…1 00 10 aaaaa aaaaa z0 dddddddddddddddd Z
1 During the idle condition, MDC and MDIO are not actively driven. During the second bit of TA and during the 16-bit data of the read and post read increment address add
frames, MDIO is driven by the MMD. At all other times, ADC and MDIO are driven by the STA bits.
IDLE (Idle Condition)
The idle condition for the MDIO is a high-impedance state.
PRE (Preamble)
At the beginning of each transaction, the STA (host) sends a sequence of at least 32 contiguous bits sent one bit at a time to the MDIO,
with 32 corresponding clock cycles on MDC, to establish the start of a frame.
ST (Start of Frame)
After the PRE the ST (consisting of two zero bits) indicates the start of the frame information.
OP (Operation Code)
The OP specifies the action to be taken, as described in Table 289.
Table 289. Operation Code
OP Descriptions
00 Set the address for a subsequent write or read frame.
01 Write to the previously set address.
11 Read from the previously set address.
10 Read from the previously set address. Then increment the address. Note that user code must increment the address in the
MDADR register.
PHYADR (Physical Address)
This address is five bits, allowing 32 unique addresses. The PHYADR is set either by 5 pins or by software.
DEVAD (Device Address)
This address is five bits and selects the device type. In the CFP standard, only MDIO Device Address 1 is supported.
TA (Turnaround)
This time is used to change from being driven by the STA to being driven by the MMD as per Figure 36.
Address/Data
The address/data field is 16 bits.
Typical Usage Sequence
Most of the MDIO interface is implemented in hardware, thus requiring minimal software effort.
1.
Enable the MDIO onto the physical pins by writing 0x0555 to GP3CON.
2. Set the frame parameters by means of MDPHY, MDCON, and MDPIN.
3. Set the interrupts with MDIEN plus the required system interrupt settings.
4. At this stage, the address and write frames can be received in MDRXD and MDADR, respectively.
5. Data must be placed in MDTXD in advance of the read or post read increment address frame so that it can be automatically inserted for
the frame.
No software intervention is required during any of the transmissions, although frame progress can be monitored with MDFRM during or
upon completion of each frame. MDSTA should not be used to check frame progress because this MMR is automatically cleared and bits
could be lost if read at an inappropriate time. If it is required to monitor frame progress, then the appropriate time to read MDSTA should
be based on interrupts or by polling the MDIO bit in INTSETP0 in the interrupt system. MDSTA should be read only once per frame.
MDIO must have the highest interrupt priority of all peripherals; otherwise, MDIO events are likely to be lost.