ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 83 of 192
A 1-bit ECC interrupt or system exception can be enabled in the ECC enable/disable register (FEEECCCONFIG), if required. If the
appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in the status register.
If there is a 2-bit ECC error and if interrupts or system exceptions are enabled in the FEEECCCONFIG register, an error is issued by the
controller. If the appropriate interrupts or system exceptions are enabled in the FEEECCCONFIG register, the appropriate flags are set in
the status register.
An ECC error is signaled by the ECC error detection/correction hardware when a flash location is read. Depending on the location which
flash (Flash 0/Flash 1) the read happens, the appropriate flags are set in the status register (ECCREADERRFLSH0, ECCREADERRFLSH1,
and so on). Note that 1-bit errors corrected meet full data sheet specifications.
If a system exception is enabled the device vectors to a hard fault or bus fault in the event of an ECC error, see the SHCSR register in the
ARM Cortex-M3 processor documentation to enable a bus fault; {see the ARM Cortex-M3 processor documentation for more
information on the SHCSR processor.
ECC Error During Read
Two separate ECCREADERR flags are present in the status register: FEESTA[10:9] and FEESTA[12:11] for Flash 0 and Flash 1. If the
interrupt is configured to be generated when an ECC error occurs, the address at which the error is detected is available for the user. If a
system exception is configured, the BFAR register contains the address for which ECC error is detected.
ECC Error During Execution of Sign Command
If there is an ECC error during the signature check, the registers are not updated. After the command is complete, ECCERRCMD flags in
FEESTA[8:7] are updated. No interrupt or system exception is generated.
Flash Protection
The following three types of protection are implemented:
•
Key protection
•
Read protection
•
Write protection
Flash Protection: Key Protection
Some of the flash controller MMRs are key protected to avoid accidental writes to these MMRs.
The user key is 0xF123F456. This key must be entered to run certain user commands, write to certain locations in flash or to enable write
access to FEECON1. Once entered, the key remains asserted unless a command is written to FEECMD. When the command starts, the
key clears automatically. If this key is entered to enable write access to FEECON1 or to enable writes to certain locations in flash, it must
be cleared by user code afterwards. To clear the key, write any value other than 0xF123F456 to FEEKEY.
Flash Protection: User Read Protection
User space read protection is provided by disabling serial wire access. The user can disable serial wire access by writing 0 to Bit 0 of FEECON1.
Serial wire access is disabled while the kernel is running; otherwise, serial wire access can prevent the kernel from running to completion.
When the kernel exits to user code, it enables serial wire access unless either of the keys at 0x3FFF4 or 0x1FFF4 is set to 0x0000003A. This
means that the device is always read protected after either key is in place and that no debug access can occur.
Flash Protection: User Write Protection
User write protection is provided to prevent accidental writes to pages in user space and to protect blocks of user code when downloading extra
code to flash. If a write or erase of a protected location is detected, the flash controller generates an interrupt if the command error/complete
interrupt are enabled. The write protection for each block is stored near the top of each block. The top four bytes are for a signature; the next
eight are reserved. The next 32-bit flash location contains the protection pattern which is copied to FEEPRO0 and FEEPRO1 at startup with
each bit protecting a block of 4 kB of flash. If no protection is specified, protection can be set by writing to FEEPRO0 and FEEPRO1.
Flash Failure Analysis Key
It may be necessary to perform failure analysis on devices that are returned by a user even though read protection is enabled. A method
has been provided to allow failure analysis of protected memory by a user flash failure analysis key (USERFAAKEY).
The user must set the key as two 32-bit values near the top of each user flash block. Supplying this key to Analog Devices allows access to
user code for debug purposes. See Figure 16 and Figure 17 for details.
