ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 129 of 192
Slave Control Register
Address: 0x40003428, Reset: 0x0000, Name: I2C1SCON
Table 184. Bit Descriptions for I2C1SCON
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R
14
STXDMA
Enable slave Tx DMA request. Set to 1 by user code to enable I
2
C slave DMA
Rx requests. Cleared by user code to disable DMA mode.
0x0
RW
13
SRXDMA
Enable slave Rx DMA request. Set to 1 by user code to enable I
2
C slave
DMA Rx requests. Cleared by user code to disable DMA mode.
0x0
RW
12
IENREPST
Repeated start interrupt enable. If 1, an interrupt is generated when the
REPSTART status bit asserts. If 0, an interrupt is not generated when the
REPSTART status bit asserts.
0x0
RW
11
SXMITDEC
Decrement slave Tx FIFO status when a byte has been transmitted. If set to 1,
the transmit FIFO status is decremented when a byte has been transmitted.
If set to 0, the transmit FIFO status is decremented when the byte is unloaded
from the FIFO into a shadow register at the start of byte transmission.
0x0
RW
10
IENSTX
Slave transmit request interrupt enable.
0x0
RW
9
IENSRX
Slave receive request interrupt enable.
0x0
RW
8
IENSTOP
Stop condition detected interrupt enable.
0x0
RW
7
NACK
No acknowledge next communication. If this bit is set, the next
communication is not acknowledged. This can be used if during a 24xx
style access, an attempt was made to write to a read only or nonexistent
location in system memory. That is the indirect address in a 24xx style
write pointed to an unwritable memory location.
0x0
RW
6
STRETCHSCL
Stretch SCL enable. Setting this bit tells the device if SCL is 0, hold it at 0; or
if SCL is 1, when it next goes to 0, hold it at 0.
0x0
RW
5
EARLYTXR
Early transmit request mode. Setting this bit enables a transmit request
just after the positive edge of the direction bit SCL clock pulse.
0x0
RW
4
GCSBCLR
General call status bit clear. The general call status and general call ID bits
are cleared when a 1 is written to this bit. The general call status and general
call ID bits are not reset by anything other than a write to this bit or a full reset.
0x0
W
3
HGCEN
Hardware general call enable. When this bit and the general call enable bit
are set, the device after receiving a general call, Address 00h, and a data
byte checks the contents of the ALT against the receive shift register. If
they match, the device has received a hardware general call. If a device
requires urgent attention from a master device without knowing which
master it requires to turn to, it can use this call. This is a call "to whom it
may concern". The device that requires attention embeds its own address
into the message. The LSB of the ALT register must always be written to a 1, as
per I
2
C January 2000 specification.
0x0
RW
2
GCEN
General call enable. This bit enables the I
2
C slave to acknowledge an I
2
C
general call, Address 0x00 (write).
0x0
RW
1
ADR10EN
Enabled 10-bit addressing. If this bit is clear, the slave can support four
slave addresses, programmed in Register I2CID0 to Register I2CID3. When
this bit is set, 10-bit addressing is enabled. One 10-bit address is supported
by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the
first byte of the address and the upper five bits must be programmed to
11110. I2CID3 and I2CID4 can be programmed with 7-bit addresses at the
same time.
0x0
RW
0
SLVEN
Slave enable. When 1, the slave is enabled. When 0, all slave state machine
flops are held in reset, and the slave is disabled.
0x0
RW
