ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 77 of 192
DMA Channel Priority Set Register
Address: 0x40010038, Reset: 0x00000000, Name: DMAPRISET
Table 98. Bit Descriptions for DMAPRISET
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved. Undefined.
0x0
R
[13:0]
CHPRISET
Configure channel for high priority. This register enables the user to configure
a DMA channel to use the high priority level. Reading the register returns
the status of the channel priority mask. Each bit of the register represents
the corresponding channel number in the DMA controller. Returns the channel
priority mask status, or sets the channel priority to high. Bit 0 corresponds
to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1.
0x0
RW
When read:
Bit C = 0: DMA Channel C is using the default priority level.
Bit C = 1: DMA Channel C is using a high priority level.
When written:
Bit C = 0: no effect. Use the DMAPRICLR register to set Channel C to the
default priority level.
Bit C = 1: Channel C uses the high priority level.
DMA Channel Priority Clear Register
Address: 0x4001003C, Reset: 0x00000000, Name: DMAPRICLR
Table 99. Bit Descriptions for DMAPRICLR
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved. Undefined.
0x0
R
[13:0]
CHPRICLR
Configure channel for default priority level. The DMAPRICLR write-only
register enables the user to configure a DMA channel to use the default
priority level. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to select
the default priority level for the specified DMA channel. Bit 0 corresponds
to DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1.
0x0
W
When written:
Bit C = 0: no effect. Use the DMAPRISET register to set Channel C to the
high priority level.
Bit C = 1: Channel C uses the default priority level.
DMA Per Channel Bus Error Register
Address: 0x4001004C, Reset: 0x00000000, Name: DMAERRCLR
Table 100. Bit Descriptions for DMAERRCLR
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved. Undefined.
0x0
R
[13:0]
ERRCLR
Bus error status. This register reads and clears the DMA bus error status.
The error status is set if the controller encountered a bus error while
performing a transfer or when it reads an invalid descriptor (whose cycle
control is 3'b000). If a bus error occurs or invalid cycle control is read on a
channel, that channel is automatically disabled by the controller. The other
channels are unaffected. Write 1 to clear the bits. Bit 0 corresponds to
DMA Channel 0, and Bit M − 1 corresponds to DMA Channel M − 1.
0x0
RW1C
When read:
Bit C = 0: no bus error/invalid cycle control occurred.
Bit C = 1: a bus error/invalid cycle control is pending.
When written:
Bit C = 0: no effect.
Bit C = 1: bit is cleared.
