ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 123 of 192
Master and Slave Shared Control Register
Address: 0x40003050, Reset: 0x0000, Name: I2C0SHCON
Table 172. Bit Descriptions for I2C0SHCON
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0000
RW
0
RESET
Write a 1 to this bit to reset the I
2
C start and stop detection circuits.
0x0
W
Setting this bit resets the LINEBUSY status bit.
Automatic Stretch Control Register
Address: 0x40003058, Reset: 0x0000, Name: I2C0ASSCL
Table 173. Bit Descriptions for I2C0ASSCL
Bits
Bit Name
Description
Reset
Access
[15:10]
RESERVED
Reserved.
0x0
R
9
SSRTSTA
Stretch timeout status bit for slave. Asserts when slave automatic stretch mode
has timed out. Cleared when this bit is read.
0x0
R
8
MSRTSTA
Stretch timeout status bit for master. Asserts when master automatic stretch
mode has timed out. Cleared when this bit is read.
0x0
R
[7:4]
SSTRCON
Automatic stretch mode control for the slave. These bits control automatic stretch
mode for slave operation. Slave stretch control allows the slave to hold the SCL
line low and to gain more time to service an interrupt, load a FIFO, or read a FIFO.
Use the timeout feature to avoid a bus lockup condition where the slave indefinitely
holds SCL low. As a slave transmitter, SCL is automatically stretched from the
negative edge of SCL if the slave Tx FIFO is empty before sending acknowledge/
no acknowledge for address byte, or before sending data for a data byte. Stretching
stops when the slave Tx FIFO is no longer empty or if a timeout occurs. As a
slave receiver, the SCL clock is automatically stretched from the negative edge of
SCL, when the slave Rx FIFO is full, before sending acknowledge/no acknowledge.
Stretching stops when slave Rx FIFO is no longer in an overflow condition or if a
timeout occurs.
0x0
RW
0000: automatic slave clock stretching disabled.
0001 to 1110: automatic slave clock stretching enabled. The timeout period is
defined by the following equation:
(
)
]
4
:7
[
I2CASSCL
2
])
8
:
10
[
CLKCON
/
UCLK
(
1
])
0
:
7
[
I2CDIV
]
8
:
15
[
I2CDIV
(
×
/
+
The I
2
C bus baud rate has no influence on slave stretch timeout period.
1111: automatic slave clock stretching enabled with indefinite timeout period.
[3:0]
MSTRCON
Automatic stretch mode control for the master. These bits control automatic
stretch mode for master operation. Master stretch control allows master to hold
the SCL line low and gain more time to service an interrupt, load a FIFO or read
a FIFO. Use the timeout feature to avoid a bus lockup condition where the
master indefinitely holds SCL low. As a master transmitter, SCL is automatically
stretched from the negative edge of SCL if the master Tx FIFO is empty before
sending acknowledge/no acknowledge for address byte, or before sending
data for a data byte. Stretching stops when the master Tx FIFO is no longer
empty or if a timeout occurs. As a master receiver, the SCL clock is automatically
stretched from the negative edge of SCL, when the master Rx FIFO is full, before
sending acknowledge/no acknowledge. Stretching stops when the master Rx
FIFO is no longer in an overflow condition or if a timeout occurs.
0x0
RW
0000: automatic master clock stretching disabled
0001 to 1110: automatic master clock stretching enabled. The timeout period is
defined by the following equation:
(
)
(
)
(
)
0]
3:
I2SCASSCL[
2
]
8
:
10
[
CLKCON
/
UCLK
1
]
0
:
7
[
I2CDIV
]
8
:
15
[
I2CDIV
×
/
+
1111: automatic master clock stretching enabled with indefinite time-out period.
