ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 25 of 192
ADC Channel Sequencer
An ADC sequencer is provided to reduce the processor overhead of sampling and reading individual channels. The ADC sequencer
allows a user to select the ADC input channels that the ADC samples, and provides a single interrupt source that is asserted when the
sequence ends. The sequencer can also be programmed to restart automatically without a delay or a programmable delay between the end
and start of sequences.
Some additional details about the sequencer include the following:
•
The sequencer reads the ADCSEQ[0:27] register to determine which channels must be included and which must be excluded from
the execution sequence.
•
ADCSEQ corresponds to ADCCHA[4:0] for the list of ADC input channels. For example, to include AIN9, set ADCSEQ[9].
•
To enable the sequencer as the Low Voltage Die Interrupt 1 source, set INTSEL[1] = 1. To enable the sequencer as the Low Voltage
Die Interrupt 0 source, set INTSEL[9] = 1.
•
To start the sequencer, set ADCSEQ[31:30] = 0x3.
•
The ADCSEQC[27:20] bits set the delay between finishing one sequence of channels and starting another sequence.
•
Normally, single-ended measurements are assumed by the ADC with AGND as the negative reference. However, for Channel 0,
Channel 2, Channel 4, and Channel 6, a differential measurement can be selected by configuring the appropriate bits in
ADCSEQC[19:0]. For example, ADCSEQC[4:0] selects the negative input when AIN0 is the positive. For single-ended
measurements using the sequencer and AIN0, set ADCSEQC[4:0] to 0x11 for AGND.
•
Take care when using the sequencer if the input buffer is enabled. The IBUFCON register controls the input buffer. If the input buffer
is enabled, all channels sampled in a sequence are sampled with the input buffer enabled. It is recommended to split sequences into
the following:
•
Sample unbuffered channels together in one sequence.
•
Sample buffered channels in a separate sequence. Note that when using the sequencer and the input buffer are enabled with
chop mode enabled, ensure that an odd number of channels are enabled in the sequence (for example, 5, 7, or 9). Two
consecutive sequences are required with the input buffer enabled with chopping. Average the two results for each enabled
channel after the second sequence for the final result.
•
Sample the internal channels (IOV
DD
/2, AV
DD
/2, and internal temperature sensor channels) separately if the ADC update rate
selected by ADCCNVC is >100 kSPS. Note that when the sequencer is enabled and includes any of these three channels, the
value in ADCCNVC does not change.
Temporarily Halting the ADC Channel Sequencer
It may be required to temporarily halt the ADC channel sequencer before it has fully completed to allow a single or multiple ADC
measurements of a channel(s) not included in the sequence.
A use case may be where the internal channels and a number of the external channels must be monitored less frequently than alarm
inputs, which must be monitored more regularly. In this case, the sequencer includes all the slower inputs and the sequencer is halted
frequently to monitor the alarm input channels. To support this, follow this sequence if ADCSEQS[2] = 1:
1.
Check ADCSEQS[2]. If this bit is set to 1, the ADC sequencer is busy and Step 1 to Step 6 must be followed. If ADCSEQS[2] = 0,
skip Step 2 to Step 6 and proceed with the single conversions.
2.
Set ADCCON[2:0] = [11]b.
3.
Set ADCSEQ[29] = 1.
4.
Wait for ADCSEQS[1] to clear to 0.
5.
After Step 4, clear ADCCON[2:0] = [00]b to disable ADC conversions.
6.
Wait for ADCSEQS[0] to clear to 0.
7.
After Step 6, the ADC sequencer is properly stalled and the ADC is ready for single conversions.
ADC DMA (Direct Memory Access)
The ADC or the ADC sequencer can be selected as the source channel for the DMA controller. This reduces processor overhead by
moving ADC results directly into SRAM with a single interrupt asserted when the required number of ADC conversions has been
completely logged to memory.
When using the ADC sequencer with the DMA controller, it is recommended to use DMA automatic request transfer types rather than
basic transfer types.
