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UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 68 of 192
INTERRUPTS
An interrupt can be produced when a transfer is complete for each DMA channel. Separate interrupt enable bits are available in the NVIC
for each of the DMA channels.
The DMA controller fetches channel control data structures located in the SRAM memory to perform data transfers. When enabled to
use DMA operation, the DMA-capable peripherals request the DMA controller for transfer. At the end of the programmed number of
DMA transfers for a channel, the DMA controller generates an interrupt corresponding to that channel. This interrupt indicates the
completion of the DMA transfer.
DMA PRIORITY
The priority of a channel is determined by its number and priority level. Each channel can have two priority levels: default or high. All
channels at high priority level have higher priority than all channels at default priority level. At the same priority level, a channel with a
lower channel number has higher priority than a channel with a higher channel number. The DMA channel priority levels can be changed
by writing into the appropriate bit in the DMAPRISET register.
CHANNEL CONTROL DATA STRUCTURE
Every channel has two control data structures associated with it: primary data structure and an alternate data structure. For simple transfer
modes, the DMA controller uses either the primary or the alternate data structure. For more complex data transfer modes, such as ping-
pong or scatter-gather, the DMA controller uses both the primary and alternate data structures. Each control data structure (primary or
alternate) occupies four 32-bit locations in the memory, as shown in Table 81. The entire channel control data structure is shown in Table 82.
Table 81. Channel Control Data Structure
Offset Name Description
0x00 SRC_END_PTR Source end pointer
0x04 DST_END_PTR Destination end pointer
0x08 CHNL_CFG Control data configuration
0x0C Reserved Reserved
Before the controller can perform a DMA transfer, the data structure related to the DMA channel must be programmed at the designated
location in system memory, SRAM.
•
The source end pointer memory location contains the end address of the source data.
•
The destination end pointer memory location contains the end address of the destination data.
•
The control data configuration memory location contains the channel configuration control data.
The programming determines the source and destination data size, the number of transfers, and the number of arbitrations.
Table 82. Memory Map of Primary and Alternate DMA Structures
Channel Primary Structures Alternate Structures
Channel 13 Reserved; set to 0 0x0DC Reserved; set to 0 0x1DC
Control 0x0D8 Control 0x1D8
Destination end pointer 0x0D4 Destination end pointer 0x1D4
Source end pointer 0x0D0 Source end pointer 0x1D0
… … … … …
Channel 1 Reserved; set to 0 0x01C Reserved; set to 0 0x11C
Control 0x018 Control 0x118
Destination end pointer 0x014 Destination end pointer 0x114
Source end pointer 0x010 Source end pointer 0x110
Channel 0 Reserved; set to 0 0x00C Reserved; set to 0 0x10C
Control 0x008 Control 0x108
Destination end pointer 0x004 Destination end pointer 0x104
Source end pointer 0x000 Source end pointer 0x100
The user must define DMA structures in their source code as shown in the examples in the Example Code: Define DMA Structures
section. After the structure has been defined, its start address must be assigned to the DMA base address pointer register, DMAPDBPTR.
Each register for each DMA channel is then at the offset address, as specified in Table 82, plus the value in the DMAPDBPTR register.