10. Parallel I/O
ÛZIATECH
62
Parallel Port Write Inhibit / Bank Address Register
0
1
2
3
4
5
6
7
Register: Write Inhibit/Bank Address
Mode: Enhanced (Bank 0)
Address: E7h
Access: Read and Write
Port Write Inhibit
0 Inactive
1 Active
Bank Address
00 Bank 0
01 Bank 1
10 Bank 2
11 Undefined
Bank
1
Bank
0
Port
5
Port
4
Port
3
Port
2
Port
1
Port
0
ZT 8907
Port Event Sense Register
Reading the event sense status of each port gets the status of each I/O port sense line.
Writing to the event sense status of each port with the corresponding bit equal to 0
clears that particular sense line.
When writing ports 0 - 5, each data bit written with a logic 0 clears its corresponding
event sense flip-flop. Each data bit of ports 0 - 5 must be written with a 1 to re-enable
the corresponding event sense input after it is cleared. Reading ports 0 - 5 returns the
event sense flip-flop status.
Parallel Port Event Sense Register
0
1
2
3
4
5
6
7
Register: Port 0 - 5 Event Sense
Mode: Enhanced (Bank 1)
Address: E0-E5h
Access: Read
Event Sense Status
0 Inactive
1 Active
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
0
1
2
3
4
5
6
7
Register: Port 0 - 5 Event Sense
Mode: Enhanced (Bank 1)
Address: E0-E5h
Access: Write
Event Sense Control
0 Clear
1 Undefined
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
ZT 8907
