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C. DIGITAL I/O ASIC SYSTEM SETUP CONSIDERATIONS
The purpose of this appendix is to illustrate precautions you should take to prevent
latchup conditions and protect inputs.
The 16C50A Digital I/O ASIC device used on the ZT 8907 is designed by Ziatech to
offer bi-directional I/O signals with or without event sense capability. This device
features low power, high speed, wide temperature operation achievable only by utilizing
CMOS technology.
Although CMOS technology offers many advantages, you must observe a few cautions
when interfacing to any CMOS parts.
•
CMOS inputs and outputs can exhibit latchup characteristics. These inherent
characteristics of any CMOS technology can result in the formation of a Silicon-
Controlled Rectifier (SCR) that appears between Vcc and ground when voltages
greater than Vcc or less than ground are applied to inputs or outputs. When this
happens, Vcc is effectively shorted to ground. The only way to remove the latchup
condition is to shut off the power supply. If a large current is allowed to flow through
the chip, its operating temperature may increase, it may exhibit intermittent
operation, or it may be damaged.
•
CMOS inputs must be protected from slow rising signals and inductive coupling on
their inputs. Failure to do so will allow a potentially large current to flow through the
chip, damaging the chip.
For more information on how the Digital I/O ASIC works, refer to the section
"
" in Chapter 10, "Parallel I/O."
Several ports of the on-board 16C50A Digital I/O ASIC device are used for monitoring
and controlling other board functions. See the section Chapter 11, "
for more information.
PREVENTING SYSTEM LATCHUP
The most common causes of latchup are:
•
Input signals applied before the input circuitry is powered, resulting in a signal to
power supply sequence mismatch
•
Input signals greater than Vcc or less than ground, resulting in a signal level
mismatch
These conditions are covered in the following topics.
