10. Parallel I/O
ÛZIATECH
63
Event Sense Manage Register
A write to this register controls the polarity of the Sense Event for I/O ports 0 - 3. Each
bit represents a nibble (4 bits) of the port. A logic 0 senses negative events, while a 1
senses positive events. The polarity of the event sense logic must be set prior to
enabling the event input logic.
A read from this register returns the event status on I/O ports 0 - 5 and the status of the
interrupt pin. Bit 7, the global interrupt pin, indicates an event sense was detected on
any of the six ports (1 = interrupt is asserted).
Parallel Port Event Sense Manage Register
0
1
2
3
4
5
6
7
Register: Event Sense Manage
Mode: Enhanced (Bank 1)
Address: E6h
Access: Read
Event Interrupt
0 Inactive
1 Active
Global Interrupt Status
0 Inactive
1 Active
Global
Port
5
Port
4
Port
3
Port
2
Port
1
Port
0
0
1
2
3
4
5
6
7
Register: Event Sense Manage
Mode: Enhanced (Bank 1)
Address: E6h
Access: Write
Event Polarity
0 Negative
1 Positive
Bits 7-4 Bits 0-3
Bits 7-4 Bits 0-3
Bits 7-4 Bits 0-3
Bits 7-4
Port 3
Port 2
Port 1
Port 0
Bits 0-3
ZT 8907
