3. STD Bus Interface
ÛZIATECH
29
STD BUS INTERRUPTS
The ZT 8907 supports both maskable and non-maskable interrupts from the STD bus.
This section discusses system level issues related to these interrupts. Refer to
Chapter 4, "
," for more information on the ZT 8907's maskable
interrupts.
Maskable Interrupts
The STD bus maskable interrupts monitored by the ZT 8907 are INTRQ* (P44),
INTRQ1* (P37), INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P6). These maskable
interrupts are configurable through the BIOS SETUP utility. Refer to Chapter 4,
"
," for details. Note that an STD 32 backplane is needed to use
INTRQ3*.
Some applications may find it necessary to share multiple interrupt sources on a single
STD bus interrupt request, as shown in the "
STD Bus Polled Interrupt Structure
" figure.
Since the interrupt controller provides a single vector for each input, it is up to the
application software to poll each possible source on the shared interrupt request signal
to determine which is requesting service. This procedure is fine for most applications,
provided that each source can be polled and that the interrupt controller is programmed
for level-triggered operation.
Some applications include edge-triggered interrupt sources. For example, the Ziatech
DOS System uses edge-triggered interrupts to support the timer used to generate the
periodic system tick. The interrupt controller inputs are independently programmable for
edge-triggered or level-triggered interrupts.
PCI interrupt sources will be programmed as level triggered. All other interrupts will be
programmed as edge triggered (to maintain PC compatibility) by the BIOS. The
selection of which interrupts are used for PCI can be changed through screen 2 of the
BIOS SETUP utility (refer to the section, "
ZT 8907-Specific SETUP Options
" in
Appendix A).
In an edge-triggered architecture, multiple interrupt sources should not share the same
interrupt request signal because it is possible to miss an interrupt request from one
source while an interrupt request from another source is being serviced. In an edge-
triggered architecture, each interrupt source requires a unique connection to the
interrupt controller, as shown in the "
STD Bus Vectored Interrupt Structure
" figure
below.
