10. Parallel I/O
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57
Three ports of the on-board 16C50A Digital I/O ASIC device are used for system
registers to monitor and control other board functions. These registers are illustrated in
Chapter 11, "
Parallel Port Functional Diagram
Internal Data Bus
Connector J5
Debounce
Logic
Output
Data Latch
Output
Buffer
Passive
Termination
Input
Buffer
Event
Detect
Logic
ZT8907
Output Latch
The output latch stores the data present on the internal data bus during a write
operation to the parallel port. The data is latched until altered by another parallel port
write, until a system reset, or until the power is turned off. The output latch is initialized
with a logical 0 during power on and system reset.
Output Buffer
The output buffer isolates the output latch from connector J5. The output buffer is an
inverting open-collector device with 12 mA of sink current and glitch-free operation
during power cycles. The inversion means that a logical 0 written to the parallel port
appears as a TTL high at connector J5, and a logical 1 written to the parallel port
appears as a TTL low at connector J5.
The open collector feature permits each parallel I/O signal to be software configured as
an input. To use a parallel port signal as an input, a logical 0 must first be written to the
output latch. This causes the output buffer to become an open-collector gate and
prevents contention with the input signal. The passive termination ranges from 25 k
Ω
minimum to 120 k
Ω
maximum. Applications needing a predictable rise time should
provide additional termination.
