3. STD Bus Interface
ÛZIATECH
27
STD-80 BUS COMPATIBILITY
Address Multiplexing
The
STD-80 Series Bus Specification
defines a multiplexing scheme to transfer address
lines A16 through A19 across the lower half of the data bus during the start of each
memory cycle. The ZT 8907 extends this concept by also transferring address lines A20
through A23 across the upper half of the data bus.
This feature is especially useful if all memory mapped STD bus boards used in the
system decode 24 bits of address. If a memory mapped board decodes fewer than
24 bits, the board appears multiple times in the 24-bit memory map. A20 is located at
port 92h. Set bit 1 to 1 for disable, 0 for enable.
Interrupts
The
STD-80 Series Bus Specification
defines a single interrupt signal, INTRQ* (P44). If
STD bus maskable interrupts are used in the application, the ZT 8907 is configurable
(through the BIOS SETUP utility, screen 2) to receive INTRQ* and three optional
interrupts: INTRQ1* (P37), INTRQ2* (P50), and INTRQ4* (P6).
STD bus peripheral boards must be capable of generating an interrupt on INTRQ1*,
INTRQ2*, and INTRQ4* to use this feature. Note that an additional interrupt, INTRQ3*,
is available in the STD 32 architecture. Chapter 4, "
," summarizes
the interrupt sources.
I/O Expansion
The
STD-80 Series Bus Specification
defines an I/O expansion signal, IOEXP, used to
reduce addressing redundancy of an I/O board decoding fewer than 16 address lines.
The ZT 8907 automatically drives this signal low when the application software performs
an STD bus I/O address in the address range FC00h through FFFFh. To use this
feature:
•
The I/O mapped STD bus board is configured to respond to an active low IOEXP.
•
The application software assigns the board to address FC00h plus the board
configuration offset.
External Masters and DMA Slaves
The ZT 8907 does not support external masters in an STD-80 architecture; an STD 32
architecture is required for external master support. The ZT 8907 supports DMA slaves
in both STD-80 and STD 32 architectures.
