10. Parallel I/O
ÛZIATECH
65
Debounce Configure Register
This register controls whether each individual port is passed through the debounce
logic. A logic 0 disables the debounce logic, and a logic 1 enables the debounce logic.
Parallel Port Debounce Configure Register
0
1
2
3
4
5
6
7
Register: Debounce Configure
Mode: Enhanced (Bank 2)
Address: E0h
Access: Read and Write
Debounce
0 Disable
1 Enable
Port
5
Port
4
Port
3
Port
2
Port
1
Port
0
ZT 8907
Debounce Duration Register (Ports 0-3)
This register controls the duration required by each input signal before it is recognized
for ports 0 - 3. The debounce times available are 4 µs, 64 µs, 1 ms, and 8 ms. A
debounce value of 00 sets 4 µs, 01 sets 64 µs, 10 sets 1 ms, and 11 sets 8 ms. This
register controls ports 0 - 3. The default value is 00 for a 4 µs debounce period.
Parallel Port Debounce Duration Register (Ports 0-3)
0
1
2
3
4
5
6
7
Register: Debounce Duration
Mode: Enhanced (Bank 2)
Address: E1h
Access: Read and Write
Duration
00 4 µs
01 64 µs
10 1 milliseconds
11 8 milliseconds
Port 3
Port 2
Port 1
Port 0
ZT 8907
