A. Board Configuration
ÛZIATECH
91
W6, W7 (Non-Maskable Interrupts)
W6 and W7 arm the AC power-fail (Chapter 15) and STD bus interrupts (Chapters 3
and 4) to generate non-maskable interrupt requests. These interrupts combine with the
PCI bus parity error interrupt before being routed to the CPU.
Bit 3 of the port 61h register enables and disables the combined interrupt source to the
CPU. Bit 2 of the port 61h register indicates whether a non-maskable interrupt was
generated by a parity error. (See the "
Non-Maskable Interrupt Structure
" figure in
Chapter 3, "STD Bus Interface").
System Register 2 (E4h), bits 0 and 1, on the Digital I/O ASIC device indicate whether a
non-maskable interrupt was generated by the STD bus or an AC power failure.
The AC input signals for the optional power-fail detection feature are available through
connector J10. See Chapter 11, "
," for more information about the
Digital I/O ASIC device.
W6
AC Power Fail NMIRQ*
In
Enabled
Out
Disabled
W7
STD Bus NMIRQ*
†
In
Enabled
Out
Disabled
W8 (STD Bus Access Disable)
Installing W8 prevents all operations from reaching the STD bus, allowing a ZT 8907
with a standard BIOS to be installed in a system as a stand-alone processor (see note
below). Configuration of this jumper sets bit 7 of the Digital I/O ASIC's System
Register 2 (E4h).
W8
Function
In
STD access inhibited
†
Out
Normal STD access
Note:
To use the ZT 8907 as a stand-alone processor, resistor packs RP1 and RP2
must be properly configured.
†
Factory default configuration
