3. STD Bus Interface
ÛZIATECH
35
There are two socketed resistor packs (RP1 and RP2) that must be installed on the
permanent master and removed from all temporary masters. These resistor packs
are located on the edge of the board between the Ziatech logo and connector J12.
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An STD 32 backplane is required. An STD-80 backplane does not support the bus
exchange protocol (DREQx* and DAKx*).
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A ZT 89CT39, or equivalent bus arbiter, is needed to manage ZT 8907 access to the
STD bus resources. The bus arbiter must be installed in Slot 'X' of the STD 32
backplane. The ZT 89CT39 must be Revision D or higher.
Multiple Master System Reset
The ZT 8907 configured for single master operation is automatically reset with a
precision voltage monitoring circuit, watchdog timer, local pushbutton reset, and the
STD bus pushbutton reset signal, PBRESET* (P48).
In response to any of these signals, the ZT 8907 initializes local peripherals and
activates the STD bus system reset, SYSRESET* (P47). STAR SYSTEM temporary
masters do not drive SYSRESET*. The SYSRESET* activation can be disabled by
removing cuttable trace CT53.
In a multiple master system, a ZT 8907 configured as a permanent master operates the
same as a ZT 8907 operating in a single master architecture. A ZT 8907 configured as
a temporary master manages reset differently.
A temporary master does not monitor PBRESET* and does not generate SYSRESET*.
Instead, a temporary master ignores PBRESET* and monitors SYSRESET*. This
enables the temporary masters to be reset when the permanent master generates
SYSRESET*. This also enables the pushbutton reset on the temporary master to reset
only the temporary master while the pushbutton on the permanent master resets the
entire system.
