4. Interrupt Controller
ÛZIATECH
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screen 2 of the SETUP utility. The PCI configuration utility then assigns
interrupts to PCI devices as needed.
Local:
Local interrupt sources include counter/timers (CTC1 and CTC2), serial
ports (COM1 and COM2), parallel port (LPT1), keyboard, math
coprocessor, real-time clock and local IDE.
PROGRAMMABLE REGISTERS
Each interrupt controller includes four initialization registers, three control registers, and
three status registers. The I/O port addressing for the interrupt controllers is given in the
"Interrupt Controller Register Addressing" table below. The base address of the master
interrupt controller is 20h and the base address of the slave interrupt controller is A0h.
Interrupt Controller Register Addressing
Address
Register
Operation
Base+0h
IRR, ISR, IPR
Read
Base+0h
ICW1
Write
Base+0h
OCW2, OCW3
Write
Base+1h
OCW1
Read/Write
Base+1h
ICW2, ICW3, ICW4
Write
ADDITIONAL INFORMATION
Refer to the
Ziatech Industrial BIOS for CompactPCI and STD 32 Systems
software
manual for more information on the operating system's use of the interrupt inputs. Refer
to the Acer Labs
FINALI-486 M1487/M1489 486 PCI Chip Set Preliminary Data Sheet
for more information on the interrupt controller registers.
