Ziatech Corporation ZT 8907 Hardware User Manual Download Page 132 | Manualshive

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C. Digital I/O ASIC System Setup Considerations

ÛZIATECH

131

Figure 6. Computer-Switched External Power Supply, Common Ground

Correct Power Supply Sequence, Correct Signal Level Match

Power

Supply

ZT 8907

Interface Cable

External

Power

Supply

Custom

Application

Vcc

1Amp

S

24

ZT8907

Digital

16C50A

I/O

ASIC

Figure 7. Computer and External Power Supply with Common Switch and Ground

Correct Power Supply Sequence, Correct Signal Level Match

Power

Supply

ZT 8907

Interface Cable

External

Power

Supply

24-Position

or

Custom

Application

Vcc

24

ZT8907

Digital

16C50A

I/O

ASIC

PROTECTING CMOS INPUTS

The most common causes of damaged inputs are:

•

Slow rise times, resulting in a ground bounce within the chip

•

Inductive coupling on I/O lines causing noise to be coupled into the chip, resulting in
intermittent operation

Each of these conditions is covered in the following topics.

Rise Times

Slow rise times on a CMOS input can easily cause the transistor to bounce between Vil
and Vih. When this oscillation occurs, the operating current goes up, resulting in
"ground bounce." Ground bounce can cause internal latchup or can cause other system
components to malfunction. A pullup termination resistor is used to increase the rise
time.

Input rise times must be kept to less than 50 ns. Given a maximum chip capacitance of
10 pF, a 5 k

Ω

resistor is the largest that could be used without additional cabling. As

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Summary of Contents for ZT 8907

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...ZT 8907 Single Board Computer with IntelDX4 Microprocessor Hardware User Manual...

Page 3: ...15 SPEAKER INTERFACE 16 AC POWER FAIL PROTECTION 16 OPTIONAL HARD DISK INTERFACE 16 OPTIONAL FLOPPY DISK INTERFACE 16 2 GETTING STARTED 17 UNPACKING 17 SYSTEM REQUIREMENTS 17 MEMORY CONFIGURATION 18 I...

Page 4: ...PROGRAMMABLE REGISTERS 53 ADDITIONAL INFORMATION 53 9 PARALLEL PRINTER PORT INTERFACE 54 PARALLEL PRINTER PORT CONFIGURATION OPTIONS 54 ADDRESS MAPPING 54 INTERRUPT SELECTION 55 PROGRAMMABLE REGISTERS...

Page 5: ...UP OPTIONS 86 JUMPER OPTIONS AND LOCATIONS 86 JUMPER DESCRIPTIONS 88 W1 MULTIPLE MASTER INTERRUPT 88 W2 PROM SRAM SELECTION 89 W3 CMOS RAM ERASE 90 W4 SRAM BATTERY BACKUP 90 W5 LOCAL KEYBOARD DISABLE...

Page 6: ...MATCH 130 PROTECTING CMOS INPUTS 131 RISE TIMES 131 INDUCTIVE COUPLING 132 ADDITIONAL INFORMATION 133 D PCI CONFIGURATION SPACE MAP 134 E ZT 8907 VS ZT 8902 TECHNICAL DIFFERENCES 136 ZT 8907 NEW FEATU...

Page 7: ...scusses the six programmable counter timers It includes a diagram of the counter timer architecture and a summary of the operating modes and the programmable registers Chapter 6 DMA Controller provide...

Page 8: ...traces on the ZT 8907 This appendix details factory default settings as well as information to tailor your board to a specific application Appendix B Specifications contains the electrical environmen...

Page 9: ...as a single master in an STD 32 architecture or as a permanent or temporary master in an STD 32 architecture ZT 89LT07 The ZT 89LT07 a low temperature version with an extended operating range for hars...

Page 10: ...s See Chapter 3 STD Bus Interface for a detailed description of the ZT 8907 interface to the STD bus architecture STD 32 Multiple Master Architecture The ZT 8907 can be configured to operate in a mult...

Page 11: ...rive interface requires one extra slot contact Ziatech Compatible with MS DOS QNX VxWorks Windows 3 1 Windows 95 and other PC compatible operating systems STD DOS and STAR BIOS options STD bus standar...

Page 12: ...EM operating manual for configuration and operating instructions Ziatech also offers software development kits for QNX and VxWorks operating systems Contact Ziatech for details or view Ziatech s web s...

Page 13: ...l Time Clock ZT8907 STD Bus Interface In an STD 32 system data transfers are dynamically sized for either 8 bits or 16 bits STD 32 compatible memory and I O boards are dynamically sensed to determine...

Page 14: ...support standard architecture boards with an 8 bit or 16 bit data path The ZT 8907 also includes many I O peripherals required for industrial control applications I O operations not decoded by local I...

Page 15: ...r power down The 24 lines are available through a 50 pin frontplane connector J5 Optional cables interface the frontplane connector to an 8 16 or 24 position I O module mounting rack such as Ziatech s...

Page 16: ...n If the watchdog timer is enabled it must be strobed at least every 500 ms Failure to strobe the watchdog timer within this time period will result in a system reset See Chapter 12 Watchdog Timer for...

Page 17: ...0 See Chapter 15 AC Power Fail for more information Optional Hard Disk Interface The ZT 8907 supports an optional local IDE hard disk interface The interface does not depend on the STD bus permitting...

Page 18: ...pped with the ZT 8907 to handle the boards SYSTEM REQUIREMENTS The ZT 8907 is designed for use with or without an STD bus backplane The ZT 8907 is electrically mechanically and functionally compatible...

Page 19: ...p to 1 Mbyte second for 8 bit data and 2 Mbytes second for 16 bit data The ZT 8907 supports the STD bus wait request signal WAITRQ to interface to memory boards with longer access time requirements th...

Page 20: ...e 640Kbyte 0 4Gbyte 4Mbyte ZT8907 I O CONFIGURATION The ZT 8907 addresses up to 64 Kbytes of I O using a 16 bit I O address The address space is divided between I O local to the board and I O on the S...

Page 21: ...902 and ZT 8907 boards differ I O Address Range Selection I O Address Range I O Usage Function 8000h FFFFh STD 32 Address Space 5000h 7FFFh PCI I O Address Space 4E70h 4FFFh PCI I O Address Space 46E8...

Page 22: ...I I O Address Space Reserved 0081h 008Fh PCI I O Address Space Onboard DMA Page Registers 0080h PCI I O Address Space Diagnostic Port 080h 0079h 007Fh PCI I O Address Space Reserved 0078h PCI I O Addr...

Page 23: ...ashers may be located between the PCB and the standoffs Be sure to retain and reinstall these washers to their original position if they are removed for any reason Also take care when installing and r...

Page 24: ...er A dynamic help line at the bottom of the screens helps you determine how to set each parameter SETUP accepts only valid parameter sets if changing one parameter invalidates another SETUP automatica...

Page 25: ...configure the appropriate peripheral devices Note that the Fixed Disk parameters used for EIDE drives include an AUTO setting which will cause SETUP to query the drive to determine the correct geometr...

Page 26: ...the value F10 to accept the current parameters or ESC to quit Ziatech Industrial BIOS Setup Utility 2482 16 63 ZT8907 1 44M BIOS SETUP Utility Screen 2 ZT 8907 Specific SETUP Options Interrupt from t...

Page 27: ...aster operation The following topic discusses STD 32 operation in greater detail STD 32 Operation Data transfers between the ZT 8907 and any STD bus memory or I O board occur eight bits at a time for...

Page 28: ...ive INTRQ and three optional interrupts INTRQ1 P37 INTRQ2 P50 and INTRQ4 P6 STD bus peripheral boards must be capable of generating an interrupt on INTRQ1 INTRQ2 and INTRQ4 to use this feature Note th...

Page 29: ...07 automatically determines the width of the data transfer at the start of each STD bus operation STD 80 compatible memory and I O boards are supported I Supports four additional STD bus interrupts IN...

Page 30: ...ocedure is fine for most applications provided that each source can be polled and that the interrupt controller is programmed for level triggered operation Some applications include edge triggered int...

Page 31: ...RQ INTRQ INTRQ INTRQ INTERRUPT STATUS PORT INTERRUPT SOURCE N INTERRUPT SOURCE 2 SOURCE 1 ZT8907 STD Bus Vectored Interrupt Structure ZT 8907 STD BUS INTRQ INTRQ INTRQ1 INTRQ2 INTERRUPT INTRQ1 INTRQ2...

Page 32: ...interrupt was generated by the STD bus or an AC power failure Bit 2 of the port 61h register indicates whether a non maskable interrupt was generated by a parity error Non Maskable Interrupt Structure...

Page 33: ...manent or temporary master operation Each master has complete access to STD bus resources and operates at full speed when the local CPU is communicating with local memory and I O It is not until the a...

Page 34: ...local I O and dual port RAM The ZT 8907 also operates at full STD bus speeds when accessing the dual port RAM It is not until the ZT 8907 and the intelligent I O board access the dual port RAM at the...

Page 35: ...system is lower system cost The intelligent I O architecture operates in both STD 80 and STD 32 bus structures Dual port RAM arbitration is local to each intelligent I O board eliminating the need fo...

Page 36: ...mer local pushbutton reset and the STD bus pushbutton reset signal PBRESET P48 In response to any of these signals the ZT 8907 initializes local peripherals and activates the STD bus system reset SYSR...

Page 37: ...e operation of the ZT 8907 The major features of the interrupt architecture are listed below 15 individually maskable interrupts Jumperless configuration Level triggered or edge triggered recognition...

Page 38: ...C2 Ch 0 4 IRQ2 Cascade 3 IRQ3 COM2 CTC 2 Ch 1 3 IRQ4 COM1 CTC 2 Ch 0 3 IRQ5 INTRQ4 CTC 2 Ch 1 3 IRQ6 INTRQ2 CTC 2 Ch 0 3 IRQ7 Local LPT CTC 2 Ch 1 5 IRQ8 Real Time Clock 3 IRQ9 INTRQ CTC 2 Ch 0 3 IRQ1...

Page 39: ...details INTERRUPT SOURCES The interrupt sources are summarized below Backplane There are five STD bus interrupts routed to the interrupt configuration logic configurable through the BIOS SETUP utilit...

Page 40: ...given in the Interrupt Controller Register Addressing table below The base address of the master interrupt controller is 20h and the base address of the slave interrupt controller is A0h Interrupt Co...

Page 41: ...are dedicated for use by the system software The architecture for these is illustrated in the PC Compatible Counter Timer CTC 1 Architecture figure on the following page The other three counter timers...

Page 42: ...ounting 3 Square wave with frequency equal to programmed count Gate enables and disables counting 4 Single pulse after programmed count expires Gate enables and disables counting 5 Single pulse after...

Page 43: ...ter timers are accessed through four I O addresses as shown in the Auxiliary Counter Timer CTC 2 Register Addressing table below Each counter timer occupies an I O port address through which the prese...

Page 44: ...counter timers Refer to the Intel 82C54 CHMOS Programmable Interval Timer data sheet for more information on the 8254 Programmable Interval Timer registers The data sheet is available online at http...

Page 45: ...ckplane DMA channel Three STD bus frontplane DMA channels DMA transfers over the 0 16 Mbyte memory address range Block DMA transfer rates of greater than 2 Mbytes sec One DMA channel for ECP parallel...

Page 46: ...backplane DMA channel unavailable to the ZT 8907 Frontplane Three channels of DMA are accessible through frontplane connector J6 The three frontplane channels are independently selectable through cutt...

Page 47: ...channels support the following three operating modes Single Mode The DMA controller executes a single transfer for each DMA cycle The count is adjusted by one for each transfer A terminal count is gen...

Page 48: ...Bus Own bit bit 5 of System Register 3 E5h is active In a single master system this bit is held active In a multiple master system this bit is software controlled to direct the DMA request to a single...

Page 49: ...the lower 16 Mbytes of DRAM memory and does not support DMA Extended Page I O Port addressing Windows 95 users with more than 16 Mbytes of RAM must ensure that their DMA controller properties are set...

Page 50: ...rrent Count Write Channel 1 Current Count Read 4 C8 Channel 2 Base Current Address Write Channel 2 Current Address Read 5 CA Channel 2 Base Current Count Write Channel 2 Current Count Read 6 CC Channe...

Page 51: ...bytes of CMOS setup RAM PROGRAMMABLE REGISTERS The real time clock includes 128 register locations These registers are accessed through I O port locations 70h and 71h A real time clock register is acc...

Page 52: ...tes 0 59 4h Time Hours 12 hour mode 1 12 4h Time Hours 24 hour mode 0 23 5h Alarm Hours 0 23 6h Day of Week 1 7 7h Date of Month 1 31 8h Month 1 12 9h Year 0 99 Ah Dh Register A D Eh 7Fh General Purpo...

Page 53: ...sted below Loopback diagnostics Does not require 12 V Baud rates up to 115 Kbaud Two independent RS 232 channels Polled and interrupt operation The serial ports are configured as DTE and are available...

Page 54: ...te 0xF8h DIV 1 Divisor Latch LSB Read Write 0xF9h DIV 0 Interrupt Control Read Write 0xF9h DIV 1 Divisor Latch MSB Read Write 0xFAh Interrupt Status Read 0xFAh FIFO Control Write 0xFBh Line Control Re...

Page 55: ...enthesis is the description for each of the modes as presented in screen 2 of the BIOS SETUP utility Parallel Port Mode Description Max Data Rate Compatibility Normal Uni directional data configuratio...

Page 56: ...dressing table below shows the I O port addressing Compatibility Extended Mode Parallel Port Interface Addressing Address Register Operation 0378h Line Printer Data Read Write 0379h Line Printer Statu...

Page 57: ...ard I O module mounting racks Event sensing and debouncing on all ports under software control FUNCTIONAL DESCRIPTION The parallel I O signals are supported through the 16C50A Digital I O ASIC a custo...

Page 58: ...cal 0 during power on and system reset Output Buffer The output buffer isolates the output latch from connector J5 The output buffer is an inverting open collector device with 12 mA of sink current an...

Page 59: ...s controlled on the 16C50A by registers E0h E1h E2h and E3h in register bank 2 An 8 MHz clock is used by the 16C50A for a timing reference thus allowing the debounce circuit to be programmed for a deb...

Page 60: ...used for controlling the device s features These register banks are selected by programming bits 6 and 7 of I O port E7h with a 00 for bank 0 a 01 for bank 1 and a 10 for bank 2 The six 8 bit ports a...

Page 61: ...d 00E4h Port 4 Event Sense Reserved Reserved 00E5h Port 5 Event Sense Reserved Reserved 00E6h Event Sense Manage Status Control 00E7h Bank Address Status Control Enhanced Bank 2 I O Port Addressing No...

Page 62: ...Control 0 Input is a logic high 1 Input is a logic low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZT 8907 Note To set a particular port and bit as an input write a logic 0 to that port and bit W...

Page 63: ...l to 0 clears that particular sense line When writing ports 0 5 each data bit written with a logic 0 clears its corresponding event sense flip flop Each data bit of ports 0 5 must be written with a 1...

Page 64: ...the interrupt pin Bit 7 the global interrupt pin indicates an event sense was detected on any of the six ports 1 interrupt is asserted Parallel Port Event Sense Manage Register 0 1 2 3 4 5 6 7 Registe...

Page 65: ...rmation Parallel Port Bank Address Register 0 1 2 3 4 5 6 7 Register Bank Address Event Sense Manage Mode Enhanced Bank 1 Address E7h Access Read Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefine...

Page 66: ...ort 1 Port 0 ZT 8907 Debounce Duration Register Ports 0 3 This register controls the duration required by each input signal before it is recognized for ports 0 3 The debounce times available are 4 s 6...

Page 67: ...period Parallel Port Debounce Duration Register Ports 4 5 0 1 2 3 4 5 6 7 Register Debounce Duration Mode Enhanced Bank 2 Address E2h Access Read and Write Duration 00 4 microseconds 01 64 microsecon...

Page 68: ...Bank Select Register Parallel Port Bank Select Register 0 1 2 3 4 5 6 7 Register Bank Select Mode Enhanced Bank 2 Address E7h Access Read and Write Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undef...

Page 69: ...he 16C50A operating instructions are outlined below The reset state for all bits is a logical 0 Unless specifically noted otherwise bits dedicated to input operation must remain programmed with a logi...

Page 70: ...Fail NMIRQ Input 0 Inactive 1 Active VMX Reserved for Ziatech Static RAM Block Selection Output 00 1st 32 Kbyte Block 01 2nd 32 Kbyte Block ZT8907F11 02 Video Multiplex Output 0 Inactive 1 Active Rese...

Page 71: ...ht Emitting Diode LED 0 Off 1 On Always write this bit to the same value as Read DO NOT change the state of this bit Register bits managed by Ziatech operating system software Note Be sure to use the...

Page 72: ...tem reset Writing a logical 1 to the watchdog timer bit arms the watchdog timer Once armed the watchdog timer must be strobed with a periodic frequency less than the timeout period or a system reset i...

Page 73: ...1 out 0e5h al or al 1 out 0e5h al popf ret ADDITIONAL INFORMATION The chip used for the watchdog timer is a DS 1238A Refer to the Dallas Semiconductor DS1705 DS1706 3 3 and 5 0 V MicroMonitor data she...

Page 74: ...termined by CPU speed Reduces STD bus traffic by keeping all PCI operations local Single slot occupancy capable VGA See the section Removing The zPM Mezzanine Card in Chapter 2 for details about the m...

Page 75: ...code shows how to turn the LED on and off The multiple master interrupt is a bi directional bit The current software state of multiple master interrupt is maintained in the multiple master state bit...

Page 76: ...ret led_off turns off the led Bit 7 controls the LED The state of bit 1 must be maintained write the same value as was read Bits 3 and 4 must be handled as shown in the input_e5 macro led_off pushf c...

Page 77: ...The ZT 8907 requires a transformer isolated AC voltage of no more than 30 V from the same source that provides the system power Ziatech s optional AC wall transformer ZT 90071 meets these requirements...

Page 78: ...ne if the AC power fail is the source of the interrupt request The three sources of non maskable interrupts are AC power fail STD bus NMIRQ PCI Parity Error Preserve any critical information into the...

Page 79: ...Socket U17 Pin 1 BIOS RECOVERY If the ZT 8907 s BIOS becomes corrupted recover it by installing a PROM programmed with the BIOS into socket U17 The PROM allows the board to boot and the BIOS to be re...

Page 80: ...remove the PROM remove jumper W2A and return jumper W4 to the A position USER STATIC RAM Installing a 128 Kbyte SRAM module into socket U17 provides four 32 Kbyte pages of SRAM memory for use by user...

Page 81: ...e SRAM module must be installed in socket U17 Perform the steps below 1 Install a 128 Kbyte SRAM module into socket U17 2 Remove all jumpers from W2 to enable the video RAM region when the system re b...

Page 82: ...res one additional slot in the STD 32 card cage HARD DISK MOUNTING The IDE hard disk is mounted to the solder side of ZT 8907 on short standoffs A cable ZT 90201 interfaces to connector J15 on the ZT...

Page 83: ...er is superior when using an onboard IDE interface because without local IDE accesses impacting the STD 32 bus other processors experience lower latency times to system wide resources Additionally the...

Page 84: ...s intended for higher volume applications where a remotely mounted floppy drive is required Optional connector J14 on the solder side of the board is loaded for access to the floppy signals A special...

Page 85: ...from the command line BIOS SETUP Screens The BIOS SETUP utility for the ZT 8907 is organized as two screens listed below Screen 1 Generic option list Options shared among all Ziatech CPUs are listed o...

Page 86: ...ge the value F10 to accept the current parameters or ESC to quit Ziatech Industrial BIOS Setup Utility 2482 16 63 ZT8907 1 44M BIOS SETUP Utility Screen 2 ZT 8907 Specific SETUP Options Interrupt from...

Page 87: ...ed as the backplane DMA channel the ZT 8907D does not support DMA channel 5 on the backplane Always set the backplane DMA parameter to channel 2 for proper operation STD 32 memory address decoding Loc...

Page 88: ...nable W6 CMOS RAM Erase W3 Flash Write Protect W9 Local Keyboard Disable W5 Multiple Master Interrupt W1 Port 80 Test Mode J12 PROM SRAM Selection W2 SRAM Battery Backup W4 STD Bus Access Disable W8 S...

Page 89: ...s have two possible selections where A is one selection and B is another This section also documents J12 which serves as both the In System Programming connector see Appendix B Specifications and the...

Page 90: ...use by user programs SRAM is selectable through bits 3 and 4 of System Register 2 E4h In screen 2 of the BIOS SETUP utility set the parameter Memory Range D8000 DFFFFh to PCI in order to access the on...

Page 91: ...ling W4B may increase battery drain when SRAM is installed Note In no case should W4 be totally unjumpered W4A W4B Function In Out SRAM is battery backed Out In SRAM is not battery backed Use this con...

Page 92: ...ther a non maskable interrupt was generated by the STD bus or an AC power failure The AC input signals for the optional power fail detection feature are available through connector J10 See Chapter 11...

Page 93: ...0 codes sent to PIO7 PIOO J5 pins 33 48 Not jumpered Normal operation RP1 RP2 Permanent Master Pullups Resistor packs RP1 and RP2 serve two related purposes detailed below 1 Permanent Master Configura...

Page 94: ...ons table provides a quick cross reference for the ZT 8907 cuttable trace descriptions that follow There are two types of cuttable traces on the ZT 8907 single option and double option Single option c...

Page 95: ...A Board Configuration ZIATECH 94 Cuttable Trace Locations CT4 CT5 CT6 CT8 B CT7 A B A CT16 A B CT17 A B CT25 A B CT39 A B CT29 A B CT46 ZT8907 CT53 S o l d e r S i d e CT47 CT48...

Page 96: ...DMA Channel 0 5 DAK Selection CT46 Out Board Revision Indicator Do not modify CT47 In Board Revision Indicator Do not modify CT48 In INTRQ4 STD Connection CT53 In STD Reset Configuration CT4 CT6 Count...

Page 97: ...tput on counter timer channel 2 is active an interrupt will be sent to the interrupt controller input IRQ15 Digital I O Event Sense When CT7B and CT8A are installed and the Digital I O ASIC chip is pr...

Page 98: ...ins 2 DRQ and 4 DAK DMA channel 7 CT16A CT17A CT25B 16 bit pins 5 DRQ and 7 DAK Alternate Frontplane DMA Settings Channel Selection Cuttable Trace Data Size Available on J6 DMA channel 5 CT39A 16 bit...

Page 99: ...as a STAR SYSTEM temporary master If you need to operate the ZT 8907 in this configuration VBAT operation with RP1 and RP2 removed contact Ziatech for assistance CT53 STD Reset Configuration By defau...

Page 100: ...RICAL AND ENVIRONMENTAL The section covers the following electrical and environmental specifications Absolute maximum ratings DC operating characteristics Battery backup characteristics STD bus loadin...

Page 101: ...4 Mbytes of DRAM and 2 Mbyte of flash Supply Voltage Vcc 4 75 to 5 25 V Supply Voltage AUX V 12 V Nominal Supply Voltage AUX V 12 V Nominal Supply Current Icc 486SX 25 0 9 A typ 1 5 A max 486SX 33 1...

Page 102: ...compatible with STD 80 systems the ZT 8907 is not guaranteed to work in all system topologies STD Bus Loading Characteristics The unit load is a convenient method for specifying the input and output d...

Page 103: ...18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40 P42 P44 P46 P48 P50 P52 P56 P54 P53 P55 P47 P49 P51 P39 P41 P43 P45 P31 P33 P35 P37 P23 P25 P27 P29 P15 P17 P19 P21 P7 P9 P11 P13 P1 P3 P5 REQ REQ REQ RE...

Page 104: ...D8 MASTER16 AENx BE3 BE2 GND W R DMAIOR EX8 START EX32 T C 5 VDC MREQx MSBURST XA31 XA30 XA29 XA28 XA27 XA26 XA25 XA24 EXRDY INTRQ3 MAKx SLBURST DMAIOW IO16 CMD EX16 BE1 BE0 MEM16 M IO D17 D16 GND IR...

Page 105: ...adapter installed The Board Dimensions figure below shows the mechanical dimensions of the ZT 8907 Length 16 51 0 063 cm 6 500 0 025 inches Width 11 43 0 038 cm 4 500 0 015 inches Thickness 0 158 0 0...

Page 106: ...the Connector Assignments table below Connector Assignments Connector Function J1 Frontplane Interrupt Connector J2 Auxiliary Counter Timer Connector J3 COM2 Connector J4 COM1 Connector J5 Parallel I...

Page 107: ...e Connector J6 Frontplane DMA J3 COM2 J4 COM1 J7 Video Keyboard Output J10 AC Power Fail J9 Printer Port J5 Parallel I O LED RESET J13 CompactPCI Local Bus Interface P E Connector J12 In System Progra...

Page 108: ...57 pin card edge connector with fingers on 0 0625 inch contact spacing The mating connector is a Viking S3VT68 5DP12 or equivalent for the solder tail or a Viking S3VT68 5DE12 or equivalent for the c...

Page 109: ...ETUP utility to be any of the following 3 4 5 6 7 9 10 11 12 or 14 Chapter 4 Interrupt Controller summarizes and illustrates the interrupt sources and the interrupt controllers programmable registers...

Page 110: ...ter Timers for more information about the auxiliary counter timer device J2 Auxiliary Counter Timer Connector Pinout Pin Signal Type Description 1 CLK0 In Out Counter timer 0 clock 2 CTL0 In Counter t...

Page 111: ...The pin assignments are shown in the J3 J4 COM2 COM1 Connectors Pinout table below The mating connector is a T B Ansley 622 1030 or equivalent J3 J4 COM2 COM1 Connectors Pinout Pin Signal Type Descri...

Page 112: ...d 29 MOD09 In Out Port E1 bit 1 5 MOD21 In Out Port E2 bit 5 30 GND Ground 6 GND Ground 31 MOD08 In Out Port E1 bit 0 7 MOD20 In Out Port E2 bit 4 32 GND Ground 8 GND Ground 33 MOD07 In Out Port E0 bi...

Page 113: ...22 1000 or equivalent Refer to Chapter 6 DMA Controller for more information J6 Frontplane DMA Connector Pinout Pin Signal Type Description 1 DRQ0 5 In DMA request 0 or 5 2 DRQ1 6 In DMA request 1 or...

Page 114: ...this connector when W5 Out The pin assignments are shown in the J7 Video Keyboard Output Connector Pinout table below The mating connector is a Samtec TCSD 08 01 N J7 Video Keyboard Output Connector P...

Page 115: ...ls are available through this connector The pin assignments are shown in the J8 Speaker Connector Pinout table below The mating connector is a Molex 39 01 0023 or equivalent The mating connector also...

Page 116: ...t See Chapter 9 Parallel Printer Port Interface for more information J9 Parallel Printer Port Interface Connector Pinout Pin Signal Type Description 1 STB Out Data strobe 2 AFD Out Autofeed 3 PD0 In o...

Page 117: ...res two Molex 39 01 0031 terminals or equivalent The AC input signals for the optional power fail detection feature are available through this connector The pin assignments are shown in the J10 AC Pow...

Page 118: ...anism The pin assignments are shown in the J11 Mezzanine Video Interface Connector Pinout table below J11 Mezzanine Video Interface Connector Pinout Pin Signal Type Description 1 RED Out VGA Red 2 GRN...

Page 119: ...served 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved J13 PCI Mezzanine Local Bus Interface Connector J13 is a 150 pin 2 mm x 2 mm female receptacle providing the PCI local bus interface to op...

Page 120: ...C BE 1 GND 17 3 3V NC NC GND PERR GND 16 DEVSEL GND 5V STOP LOCK GND 15 3 3V FRAME IRDY GND TRDY GND 14 CLK13 GND NC CLK13 NC GND 13 GNT2 CLK02 NC GND NC GND 12 REQ1 GND GNT1 CLK13 REQ2 GND 11 AD 18 A...

Page 121: ...ppy Disk Controller Interface for floppy support The pin assignments are shown in the J14 Optional Floppy Disk Interface Connector Pinout table below See Chapter 18 Optional Local Floppy Disk Interfac...

Page 122: ...Data Bit 8 5 D6 In Out Data Bit 6 6 D9 In Out Data Bit 9 7 D5 In Out Data Bit 5 8 D10 In Out Data Bit 10 9 D4 In Out Data Bit 4 10 D11 In Out Data Bit 11 11 D3 In Out Data Bit 3 12 D12 In Out Data Bit...

Page 123: ...h to make their own cables ZT 90072 Digital I O Cable ZT 90136 Serial Cable ZT 90157 Printer Cable ZT 90233 Video Keyboard Cable ZT 90201 IDE Cable ZT 90072 Digital I O Cable TB ANSLEY 171 50 50 CONDU...

Page 124: ...4 3 2 1 NA 5 9 4 8 3 7 2 6 1 622 09P 1 TRIM ALL CABLE ENDS FLUSH WITH CONNECTOR BODIES 2 USE T B ANSLEY 171 10 STRANDED 28 AWG RIBBON CABLE 3 ZIATECH APPROVAL REQUIRED FOR PARTS SUBSTITUTIONS PIN 1 T...

Page 125: ...kshell CON 00090 TB Ansley 622 2030 w o strain relief 025 square 20 pin polarized connector TB Ansley 171 20 20 conductor 28 guage stranded flat cable Pin 1 Pin 1 Stripe Pin Assignment Chart Wire No 2...

Page 126: ...1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN CONNECTION TABLE 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48...

Page 127: ...3 4 HEAT SHRINK TUBING 3 16 DIAMETER BLACK ALPHA FIT 221 3 16 PIN 1 PIN 2 FOR ABRASION PROTECTION WRAP WITH BRADY DAT 69 1 X 6 CLEAR LABEL TRIM OFF WHITE PORTION OF LABEL J1 PIN 15 SAMTEC TCSD 08 01...

Page 128: ...effectively shorted to ground The only way to remove the latchup condition is to shut off the power supply If a large current is allowed to flow through the chip its operating temperature may increas...

Page 129: ...ting in a latchup condition An external power source might be required if the external circuitry requires more than the 500 mA supplied by the cable or if a custom interface is being designed see Figu...

Page 130: ...IC Figure 2 I O Rack Vcc and Ground Supplied Externally Potential Power Supply Sequence Mismatch Signal Level Mismatch Power Supply ZT 8907 Interface Cable External Power Supply 24 Position or Custom...

Page 131: ...gure 2 Figure 3 and Figure 4 This results in signals that may be higher than Vcc or lower than ground potentially causing SCR latchup All that is generally needed is to reference one supply to the oth...

Page 132: ...most common causes of damaged inputs are Slow rise times resulting in a ground bounce within the chip Inductive coupling on I O lines causing noise to be coupled into the chip resulting in intermitte...

Page 133: ...ieved through the use of an additional power supply for the optocoupler rather than using the computer s power supply If the computer s power supply powers the optocouplers electrical isolation is def...

Page 134: ...them instead of through the diode clamps The 39 pF capacitor in conjunction with the ferrite bead forms an additional low pass filter and is entirely optional The 1 k ohm pullup ensures adequate rise...

Page 135: ...configuration space can be found in the respective manufacturer s data manuals For more information on the PCI chipset implemented on the ZT 8907 refer to the FINALi 486 M1489 M1487 486 PCI Chip Set D...

Page 136: ...ointer Vendor ID Device ID Status Command Class Code Revision ID BIST Type Header Size Cache Line Timer Latency 31 16 15 0 Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Reserved...

Page 137: ...mum and 32 Mbytes maximum onboard memory capacity An integrated 1 4 Gbyte IDE drive can be mounted to an optional onboard IDE interface on the back of the ZT 8907 Option D1 to the ZT 8907 includes a h...

Page 138: ...modified replace the 50 pin female header with a 16 pin female header for mating to J7 on the ZT 8907 ZT 8907 ZT 8902 Connector Cross Reference Connector Function Pin Count ZT 8907 Designation ZT 8902...

Page 139: ...t Flash memory Up to two 2 Mbyte AMD or Intel flash devices may be factory installed Flash memory is mapped in one contiguous block accessible from FFC00000h FFFFFFFFh if 4 Mbytes are installed Of thi...

Page 140: ...l 805 541 0488 FAX 805 541 5088 RELIABILITY Ziatech takes extra care in the design of the product in order to ensure reliability The product was designed in top down fashion using the latest in hardwa...

Page 141: ...y expired 3 Pack the board in anti static material and ship in a sturdy cardboard box with enough packing material to adequately cushion it Note Any product returned to Ziatech improperly packed will...

Page 142: ...s of International Business Machines Incorporated Windows and MS DOS are registered trademarks of Microsoft Corporation QNX is a registered trademark of QNX Software Standard Microsystems is a registe...

Page 143: ...1050 Southwood Drive San Luis Obispo CA 93401 USA Tel 805 541 0488 FAX 805 541 5088 E Mail tech_support ziatech com Internet http www ziatech com...

Page 144: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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