10. Parallel I/O
ÛZIATECH
59
To use the event inputs:
1. Determine which events are to be enabled and what polarity is to be detected, high
to low (negative) or low to high (positive) transitions.
2 Set each port to the desired polarity.
3. Enable each of the event inputs to be detected.
All I/O and external event inputs are reset to negative events, and disabled after a
Reset signal has occurred.
PROGRAMMABLE REGISTERS
The 16C50A Digital I/O ASIC supports standard and enhanced operating modes.
Standard mode is not available to ZT 8907 users; enhanced operating mode is
automatically configured by the ZT 8907 BIOS. There are three register banks used for
controlling the device's features. These register banks are selected by programming
bits 6 and 7 of I/O port E7h with a "00" for
bank 0
, a "01" for
bank 1
, and a "10" for
bank 2
. The six 8-bit ports are allocated as follows:
•
Enhanced Bank 0 I/O Port Addressing
•
Enhanced Bank 1 I/O Port Addressing
•
Enhanced Bank 2 I/O Port Addressing
Enhanced Bank 0 I/O Port Addressing
Select this register bank by programming bits 6 and 7 of I/O port E7h with a "00".
Address
Register
Read Operation
Write Operation
00E0h
Port 0 Data
MOD00-MOD07
MOD00-MOD07
00E1h
Port 1 Data
MOD00-MOD08
MOD00-MOD15
00E2h
Port 2 Data
MOD00-MOD16
MOD00-MOD23
00E3h
Port 3 Data
System Register
System Register
00E4h
Port 4 Data
System Register
System Register
00E5h
Port 5 Data
System Register
System Register
00E6h
Reserved
-----
-----
00E7h
Write Inhibit/
Bank Address
Status
Control
