10. Parallel I/O
ÛZIATECH
61
Port Data Registers
The six I/O ports assign the least significant I/O line to the least significant data line
(D0). Each bit is changed or monitored by writing or reading the individual I/O port. On a
power up or reset, the ports are reset to 0, forcing the outputs to be set high.
Parallel Port Data Registers
0
1
2
3
4
5
6
7
Register: Port 0, 1, 2, 3, 4, and 5 Data
Mode: Enhanced (Bank 0)
Address: E0h-E5h
Access: Write
Port X I/O Control
0 Output a logic high
1 Output a logic low
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
0
1
2
3
4
5
6
7
Register: Port 0, 1, 2, 3, 4, and 5 Data
Mode: Enhanced (Bank 0)
Address: E0h-E5h
Access: Read
Port X I/O Control
0 Input is a logic high
1 Input is a logic low
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
ZT 8907
Note:
To set a particular port and bit as an input, write a logic 0 to that port and bit.
Write Inhibit / Bank Address Register
The Write Inhibit/Bank Address Register is used to mask the ability to write data to the
six output ports. Power-up default has the register unmasked to allow writes to the
output ports. Writing the Write Inhibit/Bank Address Register bits 0-5 with a 1 masks I/O
ports 0 - 5, respectively, while a read returns the status of the Write Inhibit/Bank
Address Register.
Bits 7 and 6 of the register determines which bank of registers is selected. A logic 00
selects bank 0, a 01 selects bank 1, and 10 selects bank 2, respectively. A logic 11 is
an invalid state and should never be written to the Write Inhibit/Bank Address Register.
