13.3 Status Reports
13-30
IM GS210-01EN
13.3.4 Extended Event Register
Extended Event Register
EMR
EMR
LHI
LHI
LLO
LLO
TRP
RFP
ECF
ECF
EOT
EOT
TSE
EOM
Extended Event Register
:STATus:EVENt?
Condition Register
:STATus:CONDition?
14
15
13 12 11 10
9
8
14
15
13 12 11 10
9
8
SCG
6
7
5
4
3
2
1
0
6
7
5
4
3
2
1
0
TSE
EOS
EOP
RFP
EOM
OVR
OVR
Each bit in the extended event register that has a
corresponding bit in the condition register is set to 1
when the corresponding bit in the condition register
changes from 0 to 1.
Bits 9, 14, and 15
Not used (always 0)
Bit 0 EOM (End of measure)
The condition register bit is set to 0 when the GS200 is
performing measurement and set to 1 when the GS200
is not performing measurement.
Bit 1 OVR (Over range)
The condition register bit is set to 1 when the measured
result is outside of the allowable range and set to
0 when the measured result is within the allowable
range.
Bit 2 EOT (End of trace)
The condition register bit is set to 0 when the GS200 is
performing storage and set to 1 when the GS200 is not
performing storage.
Bit 3 ECF (End of create file)
The condition register bit is set to 0 when GS200 is
creating the storage result file and set to 1 when the
GS200 is not creating the storage result file.
Bit 4 TSE (Trigger sampling error)
The condition register bit is set to 0 when there is a
trigger sampling error and set to 1 when there are no
trigger sampling errors.
Bit 5 SCG (Source change)
The extended event register bit is set to 1 when the
GS200’s source value changes.
Bit 6 EOS (End of program step)
The extended event register bit is set to 1 when a
program step completes execution.
Bit 7 EOP (End of program)
The extended event register bit is set to 1 when a
program completes execution.
Bit 8 RFP (Ready for program)
The condition register bit is set to 0 when the GS200 is
getting ready to execute a program and set to 1 when
the GS200 is not getting ready to execute a program.
Bit 10 LLO (Low limiter)
The condition register bit is set to 1 when the GS200’
s low limiter has activated and is set to 0 when the
GS200’s low limiter has not activated.
Bit 11 LHI (High limiter)
The condition register bit is set to 1 when the GS200’s
high limiter has activated and set to 0 when the GS200’
s high limiter has not activated.
Bit 12 TRP (Tripped)
The extended event register bit is set to 1 when the
GS200 output trips.
Bit 13 EMR (Emergency)
The condition register bit is set to 1 when an abnormal
temperature has been detected and the GS200 needs
to be turned off.
Bit Masking
To mask a certain bit of the extended event register
so that it does not cause bit 1 (ESS) in the status
byte to change, set the corresponding bit of the
extended event enable register to 0. Do this using the
:STATus:ENABle command.
Extended Event Register and Condition
Register Operation
The extended event register indicates thirteen types of
events that occur inside the GS200. When one of the
bits in this register is 1 (and the corresponding bit of
the extended event enable register is also 1), bit 1 (EES)
in the status byte is set to 1.
Example
1. A program completes execution.
2. Bit 7 (EOP) is set to 1.
3. When bit 7 of the extended event enable register is
1, bit 1 (EES) in the status byte is set to 1.
You can also check what type of event occurred in the
GS200 by reading the contents of the extended event
register.
The condition register indicates nine types of events
that occur inside the GS200. You can check the
internal condition of the GS200 by reading the contents
of the condition register.