Yamaha CL3, Service Manual

Page: 140 / 401

CL3/CL1
140
DSP6 test items and display provided during execution (in the
right window)
1: CPU Interface (Busy) ................................................ OK
2: CPU Interface (Data Bus) ......................................... OK
3: CPU Interface (Chip Select, TXB) ............................ OK
4: CPU Interface (Address Bus) ................................... OK
5: CPU Interface (BUS W/R Reg.) ................................ OK
6: DRAM Interface (Data Bus) ...................................... OK
7: DRAM Interface (Address Bus) ................................ OK
8: DRAM Interface (Address Bus & MPR) .................... OK
9: SIO Connection...OK ................ DSP6
→
DSP6 SIO test
10: PIO Connection...OK ................ DSP6
→
DSP6 PIO test
DSP7 test items and display provided during execution (in the
right window)
1: CPU Interface (Data Bus) ......................................... OK
2: CPU Interface (Chip Select) ..................................... OK
3: CPU Interface (Address Bus) ................................... OK
4: E-RAM Interface (Data Bus) ..................................... OK
5: E-RAM Interface (Address Bus) ............................... OK
6: SIO Connection (DSP7 DSP6) ................................. OK
7: SIO Connection (DSP6 DSP7) ................................. OK
8: SIO Connection (DSP7 DSP7) ................................. OK
9: DSP7 LSI Check (DSP7 ACC) ................................. OK
The results, when judged as NG, are shown as below (for both
DSP6 and DSP7).
1) CPU Interface/DRAM, E-RAM Interface
NG: ICxxx (1) 0000 0000 XXXX 0000 0000 0000 0000 X00X
MSB LSB
IC number DSP number x = Error bit
2) SIO Connection/DSP7 → DSP6…
NG: 1 ICxxx (1) [SOxx]
→
ICxxx (1) [SIxx]
1-8. SHARC Test
Contents: Checks the communication between CPU and
SHARC.
Checks SHARC SDRAM (Address Bus, Data Bus)
Checks the FLAG line between CPU and SHARC.
Example of executing screen