Toshiba TMPR3904F, User Manual

Page: 148 / 230

TOSHIBA
TMPR3904F Rev. 2.0
140
26
Level Mode
In the level mode, the internal DREQn signal (dreq) is level-detected at a rising of the internal
clock (GCLK). If the active level is detected in the dreq signal when the channel is in the wait
status, the DMAC switches to the transfer status to start data transfer. The active level of the
DREQn signal is set up in the PosE bit of the CCRn. The active level of the DACKn signal is
the same as the active level of the DREQn signal.
If the external circuit has asserted the DREQn signal, please maintain the DREQn signal at the
active level until the DACKn signal is asserted in the I/O device access cycle. If the DREQn
signal is deasserted before the DACKn signal is asserted, the transfer request may not be
acknowledged.
If the dreq signal is at the active level at a rising of the GCLK that acknowledges the assertion of
the acknowledge signal (which is generated by the on-chip memory controllers at a memory
access in the dual address mode or in the single address mode, or is the same as the ACK* signal
at an I/O access in the dual address mode), the next data transfer is conducted immediately
afterwards. However, if a transfer request is generated on another channel with a higher
priority, a channel transit takes place.
If the dreq signal is not at the active level at a rising of the GCLK that acknowledges the
assertion of the acknowledge signal, it is understood that there is no transfer request so that a
transfer operation on another channel may be started or the bus ownership may be released to
become the wait status.
The acknowledge signal is recognized at the rising edge of the GCLK which precedes the
GCLK cycle when the final LAST* signal for a data transfer is negated.
The unit of the transfer request is designated in the TrSiz field of the CCRn.
S Y S C L K
d r e q
D R E Q n
( B u s o w n e r s h i p r e q u e s t )
( B u s o w n e r s h i p r e l e a s e
n o t i c e )
A [ 3 1 : 1 ]
• A
B E [ 3 : 0 ] *
R / W *
B S T A R T *
A c k n o w l e d g e s i g n a l
D A C K n
D a t a t r a n s f e r D a t a t r a n s f e r
T h e d r e q , t h e b u s o w n e r s h i p r e q u e s t s i g n a l , t h e b u s o w n e r s h i p r e l e a s e n o t i c e s i g n a l a n d t h e a c k n o w l e d g e
s i g n a l a r e i n t e r n a l s i g n a l s o f t h e T X 3 9 0 4 .
Fig. 10-18 Transfer Request Timing (Level Mode)