Toshiba TMPR3904F, User Manual

Page: 77 / 230

TOSHIBA
TMPR3904F Rev. 2.0
69
8.5.7 Page mode support and page hit detection
The page mode of the DRAM is a method to access while keeping asserting RAS* and changing
the column address under the fixed row address. In the DRAMC, when the bus master conducts
the burst mode access, the page mode of the DRAM is used. At the single word access, the page
mode access of the DRAM is not conducted. The DRAMC supports two modes--the fast page
mode and the hyper page mode (EDO). Selection of the fast page mode and hyper page mode is
conducted in the DPMn (n=1,0) of the channel control register.
When the row address changes (at a page hit miss), the DRAMC negates the RAS*. The page
hit miss is caused when the row address changes and the page mode access still continues. After
the page hit miss, one access cycle of the normal mode is executed and the page mode access is
continued.
8.5.8 Column address counter
A 12-bit column address counter is used for the fast page mode and the hyper page mode. When
the page mode access continues beyond the number of the column words that is set up in the
DCWn (n=0,1) of the channel control register, a page hit miss occurs. Users cannot access this
column address counter.
When the bus master conducts the burst mode access, the column address counter increments
address like as 0-4-8-C-10-... if the lower four-bit of burst starting address is 0x0. On the other
hand, it decrements address like as C-8-4-0-... if the starting address is 0xC.
8.5.9 Timing control
The timing control controls the switch timing of the row/column addresses and the timing of
RAS*/CAS* and WE*.
8.5.10 Refresh timing
The refresh supports the CAS before RAS refresh (CBR) and the CAS before RAS self refresh
(CBRS).
Normally, the CBR refresh is conducted. When a DRAM with the self refresh function is used
and the self refresh enable CBRSE of the refresh control register DREFC is 1, a self refresh is
conducted in the first refresh cycle after the TX3904 entered into the halt mode, and the refresh
timer is halted. When the halt mode is resolved, it recovers from the self refresh to the CBR
refresh. Please note that the contents of the DRAM are not retained when having shifted into the
self refresh mode using a DRAM without the self refresh function.
The refresh is conducted for Channel 0 and Channel 1 simultaneously. The refresh timer is 10
bits and programmable. Designate the number of clocks of the internal system clock with a
binary value for desired refresh cycle. For example, when the internal system clock is 50 MHz
(20 ns cycles), 15.6
µ
sec is 780 clocks so that the set-up should be (1100001100)
2
. The default
is (1100000000)
2
for 768 clocks (when @50 MHz) at 15.36
µ
sec. When using at a frequency
other than 50 MHz, the user is required to set up the appropriate number of cycles, taking the
DRAM access and refresh arbitration into consideration.