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Texas Instruments TMS320VC5509, Reference Manual

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Multichannel Selection

5-3

Multichannel Selection Modes

SPRU592E

5.2 Multichannel Selection

When a McBSP uses a time-division multiplexed (TDM) data stream while
communicating with other McBSPs or serial devices, the McBSP may need to
receive and/or transmit on only a few channels. To save memory and bus
bandwidth, you can use a multichannel selection mode to prevent data flow
in some of the channels. The McBSP has one receive multichannel selection
mode and three transmit multichannel selection modes.

Each channel partition has a dedicated channel enable register. If the
appropriate multichannel selection mode is on, each bit in the register controls
whether data flow is allowed or prevented in one of the channels that is
assigned to that partition.

Summary of Contents for TMS320VC5509

Page 1: ...TMS320VC5501 5502 5503 5507 5509 5510 DSP Multichannel Buffered Serial Port McBSP Reference Guide Literature Number SPRU592E April 2005 ...

Page 2: ...r example the following number is a hexadecimal 40 decimal 64 40h Similarly binary numbers often are shown with the suffix b For example the following number is the decimal number 4 shown in binary form 0100b If a signal or pin is active low it has an overbar For example the RESET signal is active low Related Documentation From Texas Instruments The following documents describe the C55x devices an...

Page 3: ...d timings for the device TMS320VC5509A Fixed Point Digital Signal Processor Data Manual literature number SPRS205 describes the features of the TMS320VC5509A fixed point DSP and provides signal descriptions pinouts electrical specifications and timings for the device TMS320VC5510 Fixed Point Digital Signal Processor Data Manual literature number SPRS076 describes the features of the TMS320VC5510 f...

Page 4: ... number SPRU281 describes the TMS320C55x C C Compiler This C C compiler accepts ISO standard C and C source code and produces assembly language source code for TMS320C55x devices TMS320C55x Assembly Language Tools User s Guide literature number SPRU280 describes the assembly language tools assembler linker and other tools used to develop assembly language code assembler directives macros common ob...

Page 5: ...vi This page is intentionally left blank ...

Page 6: ... 1 Clocking 2 7 2 3 2 Serial Words 2 7 2 3 3 Frames and Frame Synchronization 2 8 2 3 4 Detecting Frame Sync Pulses Even in the Reset State 2 9 2 3 5 Ignoring Unexpected Frame Sync Pulses 2 9 2 3 6 Frame Frequency 2 9 2 3 7 Maximum Frame Frequency 2 9 2 4 Frame Phases 2 11 2 4 1 Number of Phases Words and Bits Per Frame 2 11 2 4 2 Single Phase Frame Example 2 11 2 4 3 Dual Phase Frame Example 2 12...

Page 7: ... Receive Frame Sync Pulse 4 5 4 3 1 Possible Responses to Receive Frame Sync Pulses 4 5 4 3 2 Example of an Unexpected Receive Frame Sync Pulse 4 6 4 3 3 Preventing Unexpected Receive Frame Sync Pulses 4 7 4 4 Overwrite in the Transmitter 4 8 4 4 1 Example of the Overwrite Condition 4 8 4 4 2 Preventing Overwrites 4 8 4 5 Underflow in the Transmitter 4 9 4 5 1 Example of the Underflow Condition 4 ...

Page 8: ...abling Disabling the Clock Stop Mode 7 8 7 6 1 About the Clock Stop Mode 7 8 7 7 Enabling Disabling the Receive Multichannel Selection Mode 7 9 7 8 Choosing One or Two Phases for the Receive Frame 7 10 7 9 Setting the Receive Word Length s 7 11 7 9 1 About the Word Length Bits 7 12 7 10 Setting the Receive Frame Length 7 13 7 10 1 About the Selected Frame Length 7 14 7 11 Enabling Disabling the Re...

Page 9: ...ransmitter Operation 8 3 8 3 Resetting and Enabling the Transmitter 8 4 8 3 1 Reset Considerations 8 5 8 4 Setting the Transmitter Pins to Operate as McBSP Pins 8 6 8 5 Enabling Disabling the Digital Loopback Mode 8 7 8 5 1 About the Digital Loopback Mode 8 7 8 6 Enabling Disabling the Clock Stop Mode 8 8 8 6 1 About the Clock Stop Mode 8 8 8 7 Enabling Disabling Transmit Multichannel Selection 8 ...

Page 10: ...arity 8 38 8 24 1 Using CLKSP CLKXP CLKRP to Choose an Input Clock Polarity 8 39 9 General Purpose I O on the McBSP Pins 9 1 9 1 Using the McBSP Pins for GPIO 9 2 10 Emulation Power and Reset Considerations 10 1 10 1 McBSP Emulation Mode 10 2 10 2 McBSP Power Management on the TMS320VC5503 5507 5509 and TMS320VC5510 Devices 10 3 10 3 McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devi...

Page 11: ...31 12 8 Pin Control Register PCR 12 38 12 9 Receive Channel Enable Registers RCERA RCERH 12 46 12 9 1 RCERs Used in the Receive Multichannel Selection Mode 12 47 12 10 Transmit Channel Enable Registers XCERA XCERH 12 49 12 10 1 XCERs Used in a Transmit Multichannel Selection Mode 12 50 13 McBSP Register Worksheet 13 1 13 1 General Control Registers 13 2 13 2 Multichannel Selection Control Register...

Page 12: ... Synchronization and FSG Generation When GSYNC 1 CLKGDV 1 and CLKS Provides the Sample Rate Generator Input Clock 3 11 3 4 CLKG Synchronization and FSG Generation When GSYNC 1 CLKGDV 3 and CLKS Provides the Sample Rate Generator Input Clock 3 11 3 5 ST BUS and MVIP Clocking Example 3 14 3 6 Single Rate Clock Example 3 15 3 7 Double Rate Clock Example 3 16 4 1 Overrun in the McBSP Receiver 4 4 4 2 ...

Page 13: ... Data Delay 7 18 7 13 2 Bit Data Delay Used to Skip a Framing Bit 7 19 7 14 Register Bits Used to Set the Receive Sign Extension and Justification Mode 7 20 7 15 Register Bits Used to Set the Receive Interrupt Mode 7 22 7 16 Register Bits Used to Set the Receive Frame Sync Mode 7 23 7 17 Register Bit Used to Set Receive Frame Sync Polarity 7 26 7 18 Data Clocked Externally Using a Rising Edge and ...

Page 14: ... to Set the Transmit Clock Mode 8 29 8 23 Register Bit Used to Set Transmit Clock Polarity 8 31 8 24 Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge 8 33 8 25 Register Bits Used to Set the Sample Rate Generator SRG Clock Divide Down Value 8 34 8 26 Register Bit Used to Set the SRG Clock Synchronization Mode 8 36 8 27 Register Bits Used to Set the SRG...

Page 15: ... 7 4 Register Bit Used to Enable Disable the Digital Loopback Mode 7 7 7 5 Receive Signals Connected to Transmit Signals in Digital Loopback Mode 7 7 7 6 Register Bits Used to Enable Disable the Clock Stop Mode 7 8 7 7 Register Bit Used to Enable Disable the Receive Multichannel Selection Mode 7 9 7 8 Register Bit Used to Choose One or Two Phases for the Receive Frame 7 10 7 9 Register Bits Used t...

Page 16: ... 13 8 11 How to Calculate Frame Length 8 14 8 12 Register Bit Used to Enable Disable the Transmit Frame Sync Ignore Function 8 15 8 13 Register Bits Used to Set the Transmit Companding Mode 8 16 8 14 Register Bits Used to Set the Transmit Data Delay 8 17 8 15 Register Bit Used to Set the Transmit DXENA DX Delay Enabler Mode 8 20 8 16 Register Bits Used to Set the Transmit Interrupt Mode 8 21 8 17 ...

Page 17: ...MCR2 Bit Descriptions 12 35 12 11 PCR Bit Descriptions 12 39 12 12 Description For Bit x of a Receive Channel Enable Register x 0 1 2 or 15 12 46 12 13 Use of the Receive Channel Enable Registers 12 47 12 14 Description For Bit x of a Transmit Channel Enable Register x 0 1 2 or 15 12 50 12 15 Use of the Transmit Channel Enable Registers in a Transmit Multichannel Selection Mode 12 51 A 1 Document ...

Page 18: ...This chapter offers an introduction on multichannel buffered serial port McBSP for the TMS320C55x DSPs Topic Page 1 1 Introduction 1 2 1 2 Key Features of the McBSP 1 2 1 3 Block Diagram of the McBSP 1 4 1 4 McBSP Pins 1 6 Chapter 1 ...

Page 19: ... 128 channels for transmission and for reception Multichannel selection modes that enable you to allow or block transfers in each of the channels Direct interface to industry standard codecs analog interface chips AICs and other serially connected A D and D A devices Support for external generation of clock signals and frame synchronization frame sync signals A programmable sample rate generator f...

Page 20: ...en data size is referred to as a serial word or word throughout the McBSP documentation Elsewhere word is used to describe a 16 bit value µ law and A law companding The option of transmitting receiving 8 bit data with the LSB first Status bits for flagging exception error conditions The capability to use the McBSP pins as general purpose I O pins ...

Page 21: ...t McBSP Compand RSR 1 2 Compress Expand control and monitoring and frame synchronization PCR 8 RCERs 2 MCRs 2 XCRs 2 SPCRs 2 RCRs XSR 1 2 ÁÁÁÁ ÁÁÁÁ RBR 1 2 DRR 1 2 ÁÁÁÁ ÁÁÁÁ DXR 1 2 to CPU DMA controller DRR 1 2 8 XCERs RBR 1 2 Registers for data clock Registers for multichannel control and monitoring ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DSP clock generator CLKIN pin ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ McBSP internal inpu...

Page 22: ...data transmit registers DXR1 DXR2 Data written to the DXRs is shifted out to DX via the transmit shift registers XSR1 XSR2 Similarly receive data on the DR pin is shifted into the receive shift registers RSR1 RSR2 and copied into the receive buffer registers RBR1 RBR2 The contents of the RBRs is then copied to the DRRs which can be read by the CPU or the DMA controller This allows simultaneous mov...

Page 23: ...e generator general purpose input CLKS is not available on all devices and or packages Refer to the device specific data manual for information on CLKS support Devices that do not support CLKS also do not support any of the functions associated with CLKS DR I Receiving serial data general purpose input DX O Z Transmitting serial data general purpose output FSR I O Z Supplying or reflecting the rec...

Page 24: ...or receives all data Topic Page 2 1 Data Transfer Process of a McBSP 2 2 2 2 Companding Compressing and Expanding Data 2 4 2 3 Clocking and Framing Data 2 7 2 4 Frame Phases 2 11 2 5 McBSP Reception 2 15 2 6 McBSP Transmission 2 17 2 7 Interrupts and DMA Events Generated by a McBSP 2 19 Chapter 2 ...

Page 25: ...ed Receive data arrives on the DR pin and is shifted into receive shift register 1 RSR1 Once a full word is received the content of RSR1 is copied to receive buffer register 1 RBR1 only if RBR1 is not full with previous data RBR1 is then copied to data receive register 1 DRR1 unless the previous content of DRR1 has not been read by the CPU or the DMA controller If the companding feature of the McB...

Page 26: ...ctively unless the previous content of DRR1 has not been read by the CPU or the DMA controller The CPU or the DMA controller must read data from DRR2 first and then from DRR1 When DRR1 is read the next RBR to DRR copy occurs For reception the RJUST field in register SPCR1 controls the way the received data is aligned in DRR2 and DRR1 For transmission the CPU or the DMA controller must write data t...

Page 27: ...erefore be set to 8 bit mode If companding is enabled and either of the frame phases does not have an 8 bit word length companding continues as if the word length is 8 bits Figure 2 2 illustrates the companding processes When companding is chosen for the transmitter compression occurs during the process of copying data from DXR1 to XSR1 The transmit data is encoded according to the specified compa...

Page 28: ...linear data and compressing and re expanding this data This is useful only if both XCOMPAND and RCOMPAND enable the same companding format Figure 2 5 shows two methods by which the McBSP can compand internal data Data paths for these two methods are used to indicate When both the transmit and receive sections of the serial port are reset DRR1 and DXR1 are connected internally through the compandin...

Page 29: ...ler DRR1 DX XSR1 Compress Expand DR RBR1 RSR1 2 2 3 Reversing Bit Order Option to Transfer LSB First Normally the McBSP transmits or receives all data with the most significant bit MSB first However certain 8 bit data protocols that do not use companded data require the least significant bit LSB to be transferred first If you set XCOMPAND 01b in XCR2 the bit ordering of 8 bit words is reversed LSB...

Page 30: ... R X B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 ÁÁ ÁÁ Á Á ÁÁ ÁÁ Internal Internal Note The maximum frequency for the McBSP on the TMS320VC5503 5507 5509 and TMS320VC5510 devices is 1 2 the CPU clock frequency The maximum frequency for the McBSP on the TMS320VC5501 and TMS320VC5502 devices is 1 2 the frequency of the slow peripherals clock For more information on programming the frequency of the slow peripheral...

Page 31: ...a pulse occurs on a frame sync signal the McBSP begins receiving transmitting a frame of data When the next pulse occurs the McBSP receives transmits the next frame and so on Pulses on the receive frame sync signal FSR initiate frame transfers on DR Pulses on the transmit frame sync signal FSX initiate frame transfers on DX FSR or FSX can be derived from a pin at the boundary of the McBSP or deriv...

Page 32: ...ut of reset safely 2 3 5 Ignoring Unexpected Frame Sync Pulses The McBSP can be configured to ignore transmit and or receive frame synchronization pulses To have the receiver or transmitter recognize frame sync pulses clear the appropriate frame sync ignore bit RFIG 0 for the receiver XFIG 0 for the transmitter To have the receiver or transmitter ignore frame sync pulses until the desired frame le...

Page 33: ... Effectively this permits a continuous stream of data making frame synchronization pulses redundant Theoretically only an initial frame synchronization pulse is required to initiate a multipacket transfer The McBSP supports operation of the serial port in this fashion by ignoring the successive frame sync pulses Data is clocked in to the receiver or clocked out of the transmitter during every cloc...

Page 34: ...e and number of bits per word for each phase for the receiver and transmitter The maximum number of words per frame is 128 for a single phase frame and 256 for a dual phase frame The number of bits per word can be 8 12 16 20 24 or 32 bits The maximum number of bits serial port clock cycles per frame is 4096 Table 2 1 McBSP Register Bits That Determine the Number of Phases Words and Bits Per Frame ...

Page 35: ... a frame where the first phase consists of 2 words of 12 bits each followed by a second phase of three words of 8 bits each Note that the entire bit stream in the frame is contiguous There are no gaps either between words or between phases Figure 2 8 Dual Phase Frame for a McBSP Data Transfer D R X FS R X CLK R X Phase 2 word 3 Phase 2 word 2 Phase 2 word 1 ÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁ ÁÁ Á ...

Page 36: ... R X WDLEN1 010b 16 bits per word in phase 1 R X FRLEN2 0001011b 12 words in phase 2 R X WDLEN2 011b 20 bits per word in phase 2 CLKRP CLKXP 0 Receive data sampled on falling edge of internal CLKR transmit data clocked on rising edge of internal CLKX FSRP FSXP 0 Active high frame sync signal R X DATDLY 01b Data delay of 1 clock cycle 1 bit data delay Figure 2 10 shows the timing of an AC97 standar...

Page 37: ... P2W12B0 P2W12B1 DR P1W1B15 P1W1B12 P1W1B13 P1W1B14 FSR CLKR 1 bit data delay Note On the TMS320VC5501 and TMS320VC5502 devices if a 0 bit delay and an external clock are used the transfer shown in Figure 2 9 can only be achieved if the frame sync ignore bit is set to 1 If the frame sync ignore bit is 0 an additional clock cycle is required between frames ...

Page 38: ...ceive registers 1 and 2 Figure 2 12 McBSP Reception Signal Activity RRDY DR FSR CLKR Read from DRR1 b RBR1 to DRR1 copy B Read from DRR1 A RBR1 to DRR1 copy A C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 ÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁ CLKR Internal receive clock FSR Internal receive frame sync signal DR Data on DR pin RRDY Status of receiver ready bit The following process describes how data travels from the DR pi...

Page 39: ...If the word length is larger than 16 bits DRR2 and DRR1 are used and DRR2 contains the most significant bits If companding is used during the copy RCOMPAND 10b or 11b in RCR2 the 8 bit compressed data in RBR1 is expanded to a left justified 16 bit value in DRR1 If companding is disabled the data copied from RBR 1 2 to DRR 1 2 is justified and bit filled according to the RJUST bits 6 The CPU or the...

Page 40: ... DXR1 DXR1 to XSR1 copy C Write to DXR1 C DXR1 to XSR1 copy B XRDY DX FSX CLKX C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 Á Á ÁÁ ÁÁ Á Á Á Á CLKX Internal transmit clock FSX Internal transmit frame sync signal DX Data on DX pin XRDY Status of transmitter ready bit high is 1 1 The CPU or the DMA controller writes data to the data transmit register s When DXR1 is loaded the transmitter ready bit XRDY is ...

Page 41: ...or 11b in XCR2 the McBSP compresses the 16 bit data in DXR1 to 8 bit data in the µ law or A law format in XSR1 If companding is disabled the McBSP passes data from the DXR s to the XSR s without modification 3 The McBSP waits for a transmit frame sync pulse on internal FSX 4 When the pulse arrives the McBSP inserts the appropriate data delay that is selected with the XDATDLY bits of XCR2 In the pr...

Page 42: ...based upon a selected condition in the receiver of the McBSP a condition selected by the RINTM bits of SPCR1 XINT Transmit interrupt The McBSP can send a transmit interrupt request to CPU based upon a selected condition in the transmitter of the McBSP a condition selected by the XINTM bits of SPCR2 REVT Receive synchronization event An REVT signal is sent to the DMA controller when data has been r...

Page 43: ...McBSP Operation 2 20 SPRU592E This page is intentionally left blank ...

Page 44: ...s for support Topic Page 3 1 Sample Rate Generator 3 2 3 2 Clock Generation in the Sample Rate Generator 3 4 3 3 Frame Sync Generation in the Sample Rate Generator 3 9 3 4 Synchronizing Sample Rate Generator Outputs to an External Clock 3 10 3 5 Reset and Initialization Procedure for the Sample Rate Generator 3 12 3 6 Sample Rate Generator Clocking Examples 3 14 Chapter 3 ...

Page 45: ...R GSYNC synchronization and clock detection Frame pulse FWID CLKG FSG Pulse Frame FPER CLKGDV CLKSRG 0 1 CLKXP CLKX pin CLKRP CLKR pin 0 1 McBSP internal CLKSP CLKS pin CLKSM 0 1 SCLKME input clock On TMS320VC5501 and TMS320VC5502 devices the polarity of the sample rate generator input clock CLKSRG is always positive rising edge regardless of CLKRP or CLKXP McBSP internal input clock On TMS320VC55...

Page 46: ...od divide down CLKG is divided according to the FPER bits of SRGR2 to control the period from the start of a frame sync pulse to the start of the next pulse Frame sync pulse width countdown CLKG cycles are counted according to the FWID bits of SRGR1 to control the width of each frame sync pulse Note The maximum frequency for the McBSP on the TMS320VC5503 5507 5509 and TMS320VC5510 devices is 1 2 t...

Page 47: ... is driven by the internal sample rate generator output clock CLKG Note that the effects of CLKRM 1 and CLKXM 1 on the McBSP are partially affected by the use of the digital loopback mode and the clock stop SPI mode respectively The digital loopback mode is selected with the DLB bit of SPCR1 The clock stop mode is selected with the CLKSTP bits of SPCR1 When using the sample rate generator as a clo...

Page 48: ...on programming the frequency of the slow peripheral clock see the TMS320VC5501 Fixed Point Digital Signal Processor Data Manual literature number SPRS206 or the TMS320VC5502 Fixed Point Digital Signal Processor Data Manual literature number SPRS166 Other timing limitations may also apply See the device specific data manual for detailed information on the McBSP timing requirements When driving CLKX...

Page 49: ...e 3 3 Figure 3 2 Possible Inputs to the Sample Rate Generator and the Polarity Bits CLKSRG 0 1 CLKXP CLKX pin CLKRP CLKR pin 0 1 CLKSP CLKS pin CLKSM 0 1 SCLKME To clock dividers for CLKG and FSG McBSP internal input clock On TMS320VC5501 and TMS320VC5502 devices the polarity of the sample rate generator input clock CLKSRG is always positive rising edge regardless of CLKRP or CLKXP McBSP internal ...

Page 50: ...enerates rising edge on CLKG Falling edge on CLKX pin generates transitions on FSG Not all C55x devices have a CLKS pin check the device specific data manual On TMS320VC5501 and TMS320VC5502 devices the polarity of the sample rate generator input clock is always positive rising edge regardless of CLKRP or CLKXP 3 2 3 Choosing a Frequency for the Output Clock CLKG The input clock McBSP internal inp...

Page 51: ...al for detailed information on the McBSP timing requirements When driving CLKX or CLKR at the pin choose an appropriate input clock frequency When using the internal sample rate generator for CLKX and or CLKR choose an appropriate input clock frequency and divide down value CLKGDV 3 2 4 Keeping CLKG Synchronized to an External Input Clock When an external signal is selected to drive the sample rat...

Page 52: ...r case the sample rate generator must be enabled GRST 1 and the frame sync logic in the sample rate generator must be enabled FRST 1 3 3 1 Choosing the Width of the Frame Sync Pulse on FSG Each pulse on FSG has a programmable width You program the FWID bits of SRGR1 and the resulting pulse width is FWID 1 CLKG cycles where CLKG is the output clock of the sample rate generator 3 3 2 Controlling the...

Page 53: ...the input clock signal that generates CLKG no matter how long the FSR pulse is The FPER bits of SRGR2 are ignored because the frame sync period on FSG is determined by the arrival of the next frame sync pulse on the FSR pin If GSYNC 0 CLKG runs freely and is not resynchronized and the frame sync period on FSG is determined by FPER This clock synchronization is not supported on TMS320VC5501 and TMS...

Page 54: ...Provides the Sample Rate Generator Input Clock FSG needs resync CLKG resync No need to CLKG FSRP 1 FSR external FSRP 0 FSR external CLKS CLKSP 0 CLKS CLKSP 1 Figure 3 4 CLKG Synchronization and FSG Generation When GSYNC 1 CLKGDV 3 and CLKS Provides the Sample Rate Generator Input Clock FSG needs resync CLKG resync No need to CLKG FSRP 1 FSR external FSRP 0 FSR external CLKS CLKSP 0 CLKS CLKSP 1 ...

Page 55: ...SG are driven low inactive 2 Program registers that affect the sample rate generator Program the sample rate generator registers SRGR1 and SRGR2 as required for your application If necessary other control registers can be loaded with desired values provided the respective portion of the McBSP the receiver or transmitter is in reset After the sample rate generator registers are programmed wait 2 CL...

Page 56: ...eceiver and or transmitter from reset by setting RRST and or XRST 1 5 If necessary enable the frame sync logic of the sample rate generator After the required data acquisition setup is done DXR 1 2 is loaded with data set FRST 1 in SPCR2 if an internally generated frame sync pulse is required FSG is generated with an active high edge after the programmed number of CLKG clocks FPER 1 have elapsed ...

Page 57: ...nal CLKR 2 048 MHz CLKG internal FSX Internal FSG FSR FSR external 4 096 MHz CLKS W2B7 W1B1 W1B3 W1B2 W1B4 W1B5 W1B6 W1B0 W1B7 W32B0 W2B7 W1B0 W1B1 W1B2 W1B3 W1B4 W1B5 W1B6 W1B7 Á Á For this McBSP configuration DLB 0 Digital loopback mode off CLKSTP 00b Clock stop mode off and CLKRM CLKXM 1 Internal CLKR CLKX generated internally by sample rate generator GSYNC 1 Synchronize CLKG with external fram...

Page 58: ...ny divide down single rate clock CLKSP 0 Rising edge of CLKS generates CLKG and internal CLK R X Figure 3 6 Single Rate Clock Example WxBy Word x Bit y CLKS subsequent FSR DR DX subsequent FSR Internal CLKG CLKR DR DX first FSR first FSR internal CLKX Internal CLKG CLKR internal FSX Internal FSG FSR FSR external W2B7 W1B1 W1B3 W1B2 W1B4 W1B5 W1B6 W1B0 W1B7 W32B0 W2B7 W1B0 W1B1 W1B2 W1B3 W1B4 W1B5 ...

Page 59: ... CLKG and thus internal CLKR and internal CLKX is half CLKS frequency FSRM FSXM 0 Frame synchronization is externally generated The frame sync pulse is wide enough to be detected GSYNC 0 CLKS drives CLKG CLKG runs freely it is not resynchronized by a pulse on the FSR pin FSRP FSXP 0 Active high input frame sync signal RDATDLY XDATDLY 1 Data delay of one bit Figure 3 7 Double Rate Clock Example D R...

Page 60: ...on or error conditions associated with the McBSP Topic Page 4 1 McBSP Exception Error Conditions 4 2 4 2 Overrun in the Receiver 4 3 4 3 Unexpected Receive Frame Sync Pulse 4 5 4 4 Overwrite in the Transmitter 4 8 4 5 Underflow in the Transmitter 4 9 4 6 Unexpected Transmit Frame Sync Pulse 4 11 Chapter 4 ...

Page 61: ...en received Such a pulse causes data reception to abort and restart If new data has been copied into the RBR s from the RSR s since the last RBR to DRR copy this new data in the RBR s is lost This is because no RBR to DRR copy occurs the reception has been restarted Transmitter Data Overwrite This occurs when the CPU or the DMA controller overwrites data in the DXR s before the data is copied to t...

Page 62: ...R s is lost You can prevent the loss of data if DRR1 is read no later than 2 5 cycles before the end of the third word is shifted into the RSR1 Important If both DRRs are needed word length larger than 16 bits the CPU or the DMA controller must read from DRR2 first and then from DRR1 As soon as DRR1 is read the next RBR to DRR copy is initiated If DRR2 is not read first the data in DRR2 is lost No...

Page 63: ...4 2 shows the case where the overrun condition is prevented by a read from DRR1 at least 2 5 cycles before the next serial word C is completely shifted into RSR1 This ensures that an RBR1 to DRR1 copy of word B occurs before receiver attempts to transfer word C from RSR1 to RBR1 Figure 4 2 Overrun Prevented in the McBSP Receiver RBR1 to DRR1 B No RBR1 to DRR1 copy B No read from DRR1 A RBR1 to DRR...

Page 64: ...hat the receiver has been started RRST 1 in SPCR1 Case 3 in the figure is the case in which an error occurs Figure 4 3 Possible Responses to Receive Frame Sync Pulses Yes No Yes No ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ running Receiver continues Ignore frame pulse With Frame Ignore Case 1 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Previous word is lost immediately Start nex...

Page 65: ... synchronized frame Case 3 Unexpected receive frame synchronization with RFIG 0 frame sync pulses not ignored Unexpected frame sync pulses can originate from an external source or from the internal sample rate generator If a frame sync pulse starts the transfer of a new frame before the current frame is fully received this pulse is treated as an unexpected frame sync pulse and the receiver sets th...

Page 66: ...Sync Pulses Each frame transfer can be delayed by 0 1 or 2 CLKR cycles depending on the value in the RDATDLY bits of RCR2 For each possible data delay Figure 4 5 shows when a new frame sync pulse on FSR can safely occur relative to the last bit of the current frame Figure 4 5 Proper Positioning of Frame Sync Pulses For 2 bit delay Next frame sync pulse here or later is OK For 1 bit delay Next fram...

Page 67: ...h D before C is copied to XSR1 Thus C is never transmitted on DX Figure 4 6 Data in the McBSP Transmitter Overwritten and Therefore Not Transmitted Write to DXR1 D ÁÁ ÁÁ Á Á Write to DXR1 E DXR1 to XSR1 copy D Write to DXR1 C D5 D6 D7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 XRDY DX FSX CLKX ÁÁ ÁÁ ÁÁ ÁÁ 4 4 2 Preventing Overwrites You can prevent CPU overwrites by making the CPU Poll for XRDY 1 in SPCR2 befo...

Page 68: ... DXR2 first and then load DXR1 As soon as DXR1 is loaded the contents of both DXRs are copied to the transmit shift registers XSRs If DXR2 is not loaded first the previous content of DXR2 is passed to the XSR2 XEMPTY is deactivated XEMPTY 1 when a new word in DXR1 is transferred to XSR1 If FSXM 1 in PCR and FSGM 0 in SRGR2 the transmitter generates a single internal FSX pulse in response to a DXR ...

Page 69: ...4 B5 B6 B7 A0 A1 XRDY DX FSX CLKX ÁÁ ÁÁ Write to DXR1 C DXR1 to XSR1 copy B 4 5 2 Example of Preventing the Underflow Condition Figure 4 8 shows the case of writing to DXR1 just before an underflow condition would otherwise occur After B is transmitted C is written to DXR1 before the next frame sync pulse As a result there is no underflow B is not transmitted twice Figure 4 8 Underflow Prevented i...

Page 70: ...c Pulses Figure 4 9 shows the decision tree that the transmitter uses to handle all incoming frame sync pulses The figure assumes that the transmitter has been started XRST 1 in SPCR2 Case 3 in the figure is the case in which an error occurs Figure 4 9 Possible Responses to Transmit Frame Sync Pulses Yes No Yes No running Transmit stays Ignore frame pulse With Frame Ignore Case 1 transfer Restart ...

Page 71: ...chronization with XFIG 0 frame sync pulses not ignored Unexpected frame sync pulses can originate from an external source or from the internal sample rate generator If a frame sync pulse starts the transfer of a new frame before the current frame is fully transmitted this pulse is treated as an unexpected frame sync pulse and the transmitter sets the transmit frame sync error bit XSYNCERR in SPCR2...

Page 72: ...es Each frame transfer can be delayed by 0 1 or 2 CLKX cycles depending on the value in the XDATDLY bits of XCR2 For each possible data delay Figure 4 11 shows when a new frame sync pulse on FSX can safely occur relative to the last bit of the current frame Figure 4 11 Proper Positioning of Frame Sync Pulses For 2 bit delay Next frame sync pulse here or later is OK For 1 bit delay Next frame sync ...

Page 73: ...Unexpected Transmit Frame Sync Pulse McBSP Exception Error Conditions 4 14 SPRU592E This page is intentionally left blank ...

Page 74: ...des Topic Page 5 1 Channels Blocks and Partitions 5 2 5 2 Multichannel Selection 5 3 5 3 Configuring a Frame for Multichannel Selection 5 4 5 4 Using Two Partitions 5 5 5 5 Using Eight Partitions 5 8 5 6 Receive Multichannel Selection Mode 5 10 5 7 Transmit Multichannel Selection Mode 5 11 5 8 Using Interrupts Between Block Transfers 5 15 Chapter 5 ...

Page 75: ...lock 2 Channels 32 47 Block 3 Channels 48 63 Block 4 Channels 64 79 Block 5 Channels 80 95 Block 6 Channels 96 111 Block 7 Channels 112 127 The blocks are assigned to partitions according to the selected partition mode In the 2 partition mode you assign one even numbered block 0 2 4 or 6 to partition A and one odd numbered block 1 3 5 or 7 to partition B In the 8 partition mode blocks 0 through 7 ...

Page 76: ...nels To save memory and bus bandwidth you can use a multichannel selection mode to prevent data flow in some of the channels The McBSP has one receive multichannel selection mode and three transmit multichannel selection modes Each channel partition has a dedicated channel enable register If the appropriate multichannel selection mode is on each bit in the register controls whether data flow is al...

Page 77: ...eive frame length must be at least 40 RFRLEN1 39 If XFRLEN1 39 in this case the receiver creates 40 time slots per frame but only receives data during time slots 0 15 and 39 of each frame Note The frame sync pulse can be generated internally by the sample rate gener ator or it can be supplied externally by another source In a multichannel mode configuration with external frame sync generation the ...

Page 78: ...Similarly any two of the eight transmit channel blocks up 32 enabled transmit channels can be assigned to transmit partitions A and B For reception Assign an even numbered channel block 0 2 4 or 6 to receive partition A by writing to the RPABLK bits In the receive multichannel selection mode the channels in this partition are controlled by receive channel enable register A RCERA Assign an odd numb...

Page 79: ...se more than 32 channels you can change which channel blocks are assigned to partitions A and B during the course of a data transfer However these changes must be carefully timed While a partition is being transferred its the associated block assignment bits cannot be modified and its associated channel enable register cannot be modified For example if block 3 is being transferred and block 3 is a...

Page 80: ...t for partition B Figure 5 2 Reassigning Channel Blocks Throughout a McBSP Data Transfer 0 15 112 127 96 111 80 95 64 79 48 63 32 47 16 31 0 15 Block Channels FS R X ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 1 2 3 4 5 6 7 0 Partition A B A B A B A B A Block 2 assigned to partition A Block 4 assigned to partition A Block 6 assigned to partition A Block 0 assigned to partition A Block 3 ...

Page 81: ...s transferred beginning with the channels in partition A In the 8 partition mode the R X PABLK and R X PBBLK bits are ignored and the 16 channel blocks are assigned to the partitions as shown in Table 5 1 and Table 5 2 These assignments cannot be changed The tables also show the registers used to control the channels in the partitions Table 5 1 Receive Channel Assignment and Control When Eight Rec...

Page 82: ...annels 64 through 79 XCERE F Block 5 channels 80 through 95 XCERF G Block 6 channels 96 through 111 XCERG H Block 7 channels 112 through 127 XCERH Figure 5 3 shows an example of the McBSP using the 8 partition mode In response to a frame sync pulse the McBSP begins a frame transfer with partition A and then activates B C D E F G and H to complete a 128 word frame Figure 5 3 McBSP Data Transfer in ...

Page 83: ...by the RMCME bit of MCR1 If a receive channel is disabled any bits received in that channel are passed only as far as the receive buffer register s RBR s The receiver does not copy the content of the RBR s to the DRR s and as a result does not set the receiver ready bit RRDY Therefore no DMA synchronization event REVT is generated and if the receiver interrupt mode depends on RRDY RINTM 00b no int...

Page 84: ...are selected in the appropriate transmit channel enable registers XCERs If enabled a channel in this mode is also unmasked The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs 10b All channels are enabled but they are masked unless they are selected in the appropriate transmit channel enable registers XCERs The XMCME bit of MCR2 determines whether 32 channel...

Page 85: ...ing Unmasking For transmission a channel can be Enabled and unmasked transmission can begin and can be completed Enabled but masked transmission can begin but cannot be completed Disabled transmission cannot occur The following definitions explain the channel control options Enabled channel A channel that can begin transmission by passing data from the data transmit register s DXR s to the transmi...

Page 86: ...configured as follows XPHASE 0 Single phase frame required for multichannel selection modes XFRLEN1 0000011b 4 words per frame XWDLEN1 000b 8 bits per word XMCME 0 2 partition mode only partitions A and B used In the case where XMCM 11b transmission and reception are symmetric which means the corresponding bits for the receiver RPHASE RFRLEN1 RWDLEN1 and RMCME must have the same values as XPHASE X...

Page 87: ...nabled only 1 and 3 unmasked ÁÁ ÁÁ Write to DXR1 W3 DXR1 to XSR1 copy W0 Write to DXR1 W1 DXR1 to XSR1 copy W1 Write to DXR1 W2 XRDY DXR1 to XSR1 copy W3 DXR1 to XSR1 copy W2 W3 Internal FSX Á Á Á Á W1 Á Á Á Á DX d XMCM 11b RPABLK 00b XPABLK X RCERA 000Ah XCERA 0008h Receive channels 1 and 3 enabled transmit channels 1 and 3 enabled but only 3 unmasked DXR1 to XSR1 copy W1 XRDY DXR1 to XSR1 copy W...

Page 88: ...rupt RINT request is generated at the end of each block transfer if RINTM 01b In any of the transmit multichannel selection modes a transmit interrupt XINT request is generated at the end of each block transfer if XINTM 01b When RINTM XINTM 01b no interrupt is generated unless a multichannel selection mode is on These interrupt pulses are active high and last for 2 McBSP internal input clock cycle...

Page 89: ...Using Interrupts Between Block Transfers Multichannel Selection Modes 5 16 SPRU592E This page is intentionally left blank ...

Page 90: ...ices using the SPI protocol Topic Page 6 1 SPI Protocol 6 2 6 2 Clock Stop Mode 6 3 6 3 Bits Used to Enable and Configure the Clock Stop Mode 6 4 6 4 Clock Stop Mode Timing Diagrams 6 6 6 5 Procedure for Configuring a McBSP for SPI Operation 6 8 6 6 McBSP as the SPI Master 6 10 6 7 McBSP as an SPI Slave 6 13 Chapter 6 ...

Page 91: ...e 6 1 Figure 6 1 Typical SPI Interface SPI compliant SCK MOSI MISO SS SPI compliant slave SCK MOSI MISO SS master The master device controls the flow of communication by providing shift clock and slave enable signals The slave enable signal is an optional active low signal that enables the serial data input and output of the slave device the device not sending out the clock In the absence of a ded...

Page 92: ... synchronized so that the McBSP functions as an SPI master or slave device The transmit clock signal CLKX corresponds to the serial clock signal SCK of the SPI protocol while the transmit frame synchronization signal FSX is used as the slave enable signal SS The receive clock signal CLKR and receive frame synchronization signal FSR are not used in the clock stop mode because these signals are inte...

Page 93: ...LKX signal CLKRP bit of PCR This bit determines the polarity of the CLKR signal CLKXM bit of PCR This bit determines whether CLKX is an input signal McBSP as slave or an output signal McBSP as master XPHASE bit of XCR2 You must use a single phase transmit frame XPHASE 0 RPHASE bit of RCR2 You must use a single phase receive frame RPHASE 0 XFRLEN1 bits of XCR1 You must use a transmit frame length o...

Page 94: ...on the rising edge of CLKX and receives data on the falling edge of CLKR CLKSTP 11b CLKXP 0 CLKRP 1 Low inactive state with delay The McBSP transmits data one half cycle ahead of the rising edge of CLKX and receives data on the rising edge of CLKR CLKSTP 10b CLKXP 1 CLKRP 0 High inactive state without delay The McBSP transmits data on the falling edge of CLKX and receives data on the rising edge o...

Page 95: ... a packet transfer When consecutive packet transfers are performed this leads to a minimum idle time of two bit periods between each packet transfer Figure 6 2 SPI Transfer With CLKSTP 10b no clock delay CLKXP 0 CLKRP 0 Á Á Á Á Á Á Á Á B1 B2 B4 B3 B0 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 FSX SS DX or DR MOSI from master CLKX SCK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á...

Page 96: ...OSI DX If the McBSP is the SPI slave CLKXM 0 MOSI DR 2 If the McBSP is the SPI master CLKXM 1 MISO DR If the McBSP is the SPI slave CLKXM 0 MISO DX Figure 6 5 SPI Transfer With CLKSTP 11b clock delay CLKXP 1 CLKRP 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ B1 B2 B4 B3 B0 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 FSX SS CLKX SCK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á ÁÁ DX or...

Page 97: ...PCR2 Make sure that during the write to SPCR2 you only modify GRST Otherwise you will modify the McBSP configuration you selected in the previous step 5 Enable the transmitter and receiver After the sample rate generator is released from reset wait two sample rate generator clock periods for the McBSP logic to stabilize If the CPU services the McBSP transmit and receive buffers then you can immedi...

Page 98: ... Clock Stop Mode SPRU592E 6 If necessary enable the frame sync logic of the sample rate generator After the required data acquisition setup is done DXR 1 2 is loaded with data set FRST 1 if an internally generated frame sync pulse is required that is if the McBSP is the SPI master ...

Page 99: ... as a master the transmit output signal DX is used as the MOSI signal of the SPI protocol and the receive input signal DR is used as the MISO signal Figure 6 6 McBSP as the SPI Master McBSP master CLKX DX DR FSX SPI compliant slave SCK MOSI MISO SS The register bit values required to configure the McBSP as a master are listed in Table 6 3 After the table are more details about the configuration re...

Page 100: ... 0 The transmitter drives a frame sync pulse on the FSX pin every time data is transferred from DXR1 to XSR1 FSXP 1 The FSX pin is active low XDATDLY 01b RDATDLY 01b This setting provides the correct setup time on the FSX signal When the McBSP functions as the SPI master it controls the transmission of data by producing the serial clock signal The clock signal on the CLKX pin is enabled only durin...

Page 101: ...ted FSGM 0 The polarity of the FSX pin is programmable high or low however in most cases the pin should be configured active low When the McBSP is configured as described for SPI master operation the bit fields for frame sync pulse width FWID and frame sync period FPER are overridden and custom frame sync waveforms are not allowed The signal becomes active before the first bit of a packet transfer...

Page 102: ...P used as a slave is shown in Figure 6 7 When the McBSP is configured as a slave DX is used as the MISO signal and DR is used as the MOSI signal Figure 6 7 McBSP as an SPI Slave McBSP slave CLKX DX DR FSX SPI compliant master SCK MISO MOSI SS The register bit values required to configure the McBSP as a slave are listed in Table 6 4 ...

Page 103: ...efore generating CLKG FSXM 0 The FSX pin is an input pin so that it can be driven by the SPI master FSXP 1 The FSX pin is active low XDATDLY 00b RDATDLY 00b These bits must be 0s for SPI slave operation When the McBSP is used as an SPI slave the master clock and slave enable signals are generated externally by a master device Accordingly the CLKX and FSX pins must be configured as inputs The CLKX ...

Page 104: ...his means that the master device must assert the slave enable signal at the beginning of each transfer and deassert the signal after the completion of each packet transfer the slave enable signal cannot remain active between transfers The data delay parameters of the McBSP must be set to 0 for proper SPI slave operation A value of 1 or 2 is undefined in the clock stop mode ...

Page 105: ...SPI Operation Using the Clock Stop Mode 6 16 SPRU592E This page is intentionally left blank ...

Page 106: ... 7 10 Setting the Receive Frame Length 7 13 7 11 Enabling Disabling the Receive Frame Sync Ignore Function 7 15 7 12 Setting the Receive Companding Mode 7 16 7 13 Setting the Receive Data Delay 7 17 7 14 Setting the Receive Sign Extension and Justification Mode 7 20 7 15 Setting the Receive Interrupt Mode 7 22 7 16 Setting the Receive Frame Sync Mode 7 23 7 17 Setting the Receive Frame Sync Polari...

Page 107: ...7 2 SPRU592E 7 1 Configuring the McBSP Receiver You must perform the following three steps to configure the McBSP receiver 1 Place the McBSP receiver in reset 2 Program the McBSP registers for the desired receiver operation 3 Take the receiver out of reset ...

Page 108: ...l loopback mode J Enable disable the clock stop mode J Enable disable the receive multichannel selection mode Data behavior J Choose one or two phases for the receive frame J Set the receive word length s J Set the receive frame length J Enable disable the receive frame sync ignore function J Set the receive companding mode J Set the receive data delay J Set the receive sign extension and justific...

Page 109: ...eset state RRST 1 The serial port receiver is enabled SPCR2 6 GRST Sample Rate Generator Reset GRST 0 Sample rate generator is reset If GRST 0 due to a DSP reset CLKG is driven by the McBSP internal input clock divided by 2 and FSG is driven low inactive If GRST 0 due to program code CLKG and FSG are both driven low inactive GRST 1 Sample rate generator is enabled CLKG is driven according to the c...

Page 110: ...ing the GRST bit in SPCR2 Table 7 2 shows the state of McBSP pins when the serial port is reset due to a DSP reset and a direct receiver transmitter reset Table 7 2 Reset State of Each McBSP Pin Pin Possible State s State Forced By DSP Reset State Forced By Receiver Transmitter Reset Receiver Reset RRST 0 and GRST 1 DR I Input Input CLKR I O Z Input Known state if Input CLKR running if output FSR ...

Page 111: ...W Write n Value after reset Table 7 3 Register Bit Used to Set Receiver Pins to Operate as McBSP Pins Register Bit Name Function PCR 12 RIOEN Receive I O enable This bit is only applicable when the receiver is in the reset state RRST 0 in SPCR1 RIOEN 0 The DR FSR CLKR and CLKS pins are configured as serial port pins and do not function as general purpose I O pins RIOEN 1 The DR pin is a general pu...

Page 112: ...5 DLB Digital Loopback Mode DLB 0 Digital loopback mode is disabled DLB 1 Digital loopback mode is enabled 7 5 1 About the Digital Loopback Mode In the digital loopback mode the receive signals are connected internally through multiplexers to the corresponding transmit signals as shown in Table 7 5 This mode allows testing of serial port code with a single DSP device the McBSP receives the data it...

Page 113: ...de enabled with clock delay 7 6 1 About the Clock Stop Mode The clock stop mode supports the SPI master slave protocol If you will not be using the SPI protocol you can clear CLKSTP to disable the clock stop mode In the clock stop mode the clock stops at the end of each data transfer At the beginning of each data transfer the clock starts immediately CLKSTP 10b or after a half cycle delay CLKSTP 1...

Page 114: ...5 1 0 RMCM R W 0 Legend R Read W Write n Value after reset Table 7 7 Register Bit Used to Enable Disable the Receive Multichannel Selection Mode Register Bit Name Function MCR1 0 RMCM Receive Multichannel Selection Mode RMCM 0 The mode is disabled All 128 channels are enabled RMCM 1 The mode is enabled Channels can be individually enabled or disabled The only channels enabled are those selected in...

Page 115: ...me has one or two phases Figure 7 6 Register Bit Used to Choose One or Two Phases for the Receive Frame RCR2 15 14 0 RPHASE R W 0 Legend R Read W Write n Value after reset Table 7 8 Register Bit Used to Choose One or Two Phases for the Receive Frame Register Bit Name Function RCR2 15 RPHASE Receive phase number Specifies whether the receive frame has one or two phases RPHASE 0 Single phase frame R...

Page 116: ...e after reset Table 7 9 Register Bits Used to Set the Receive Word Length s Register Bit Name Function RCR1 7 5 RWDLEN1 Receive word length 1 Specifies the length of every serial word in phase 1 of the receive frame RWDLEN1 000 8 bits RWDLEN1 001 12 bits RWDLEN1 010 16 bits RWDLEN1 011 20 bits RWDLEN1 100 24 bits RWDLEN1 101 32 bits RWDLEN1 11X Reserved RCR2 7 5 RWDLEN2 Receive word length 2 If a ...

Page 117: ...ng on the value that you load into the RPHASE bit If a single phase frame is selected RWDLEN1 selects the length for every serial word received in the frame and RWDLEN2 is ignored If a dual phase frame is selected RWDLEN1 determines the length of the serial words in phase 1 of the frame and RWDLEN2 determines the word length in phase 2 of the frame ...

Page 118: ...alue after reset Table 7 10 Register Bits Used to Set the Receive Frame Length Register Bit Name Function RCR1 14 8 RFRLEN1 Receive frame length 1 RFRLEN1 1 is the number of serial words in phase 1 of the receive frame RFRLEN1 000 0000 1 word in phase 1 RFRLEN1 000 0001 2 words in phase 1 RFRLEN1 111 1111 128 words in phase 1 RCR2 14 8 RFRLEN2 Receive frame length 2 If a dual phase frame is select...

Page 119: ...h of phase 1 plus the length of phase 2 The 7 bit RFRLEN fields allow up to 128 words per phase See Table 7 11 for a summary of how to calculate the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization pulse Note Program the RFRLEN fields with w minus 1 where w represents the number of words per phase For example if you want a phas...

Page 120: ...e Function Register Bit Name Function RCR2 2 RFIG Receive Frame Sync Ignore RFIG 0 An unexpected receive frame sync pulse causes the McBSP to restart the frame transfer RFIG 1 The McBSP ignores unexpected receive frame sync pulses 7 11 1 About Unexpected Frame Sync Pulses and the Frame Sync Ignore Function If a frame synchronization frame sync pulse starts the transfer of a new frame before the cu...

Page 121: ...gend R Read W Write n Value after reset Table 7 13 Register Bits Used to Set the Receive Companding Mode Register Bit Name Function RCR2 4 3 RCOMPAND Receive companding mode Modes other than 00b are enabled only when the appropriate RWDLEN is 000b indicating 8 bit data RCOMPAND 00 No companding any size data MSB received first RCOMPAND 01 No companding 8 bit data LSB received first for details scr...

Page 122: ...data delay RDATDLY 10 2 bit data delay RDATDLY 11 Reserved 7 13 1 About the Data Delay The start of a frame is defined by the first clock cycle in which frame synchronization is found to be active The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required This delay is called data delay RDATDLY specifies the data delay for reception The...

Page 123: ...ge of CLKR where an active high internal FSR is detected However data transmission must begin on the rising edge of the internal CLKX clock that generated the frame synchronization Therefore the first data bit is assumed to be present in XSR1 and thus on DX The transmitter then asynchronously detects the frame sync signal FSX going active high and immediately starts driving the first bit to be tra...

Page 124: ...Setting the Receive Data Delay 7 19 Receiver Configuration SPRU592E Figure 7 13 2 Bit Data Delay Used to Skip a Framing Bit DR Framing bit B5 B6 B7 FSR CLKR Á Á 2 bit delay ...

Page 125: ...UST 01 Right justify data and sign extend it into the MSBs in DRR 1 2 RJUST 10 Left justify data and zero fill LSBs in DRR 1 2 RJUST 11 Reserved 7 14 1 About the Sign Extension and the Justification RJUST in SPCR1 selects whether data in RBR 1 2 is right or left justified with respect to the MSB in DRR 1 2 and how unused bits in DRR 1 2 are filled with zeros or with sign bits Table 7 16 and Table ...

Page 126: ...92E Table 7 17 Example Use of RJUST Field With 20 Bit Data Value 0xABCDE RJUST Justification Extension Value in DRR2 Value in DRR1 00b Right Zero fill MSBs 000Ah BCDEh 01b Right Sign extend data into MSBs FFFAh BCDEh 10b Left Zero fill LSBs ABCDh E000h 11b Reserved Reserved Reserved Reserved ...

Page 127: ...The receive interrupt RINT signals the CPU of changes to the serial port status Four options exist for configuring this interrupt The options are set by the receive interrupt mode bits RINTM in SPCR1 RINTM 00b Interrupt on every serial word by tracking the RRDY bit in SPCR1 Note that regardless of the value of RINTM RRDY can be read to detect the RRDY 1 condition RINTM 01b In the multichannel sele...

Page 128: ...CR1 15 14 13 12 11 10 0 DLB CLKSTP R W 0 R W 00 Legend R Read W Write n Value after reset Table 7 19 Register Bits Used to Set the Receive Frame Sync Mode Register Bit Name Function PCR 10 FSRM Receive Frame Synchronization Mode FSRM 0 Receive frame synchronization is supplied by an external source via the FSR pin FSRM 1 Receive frame synchronization is supplied by the sample rate generator FSR is...

Page 129: ...to a pulse on the FSR pin The frame sync period defined in FPER is ignored SPCR1 15 DLB Digital Loopback Mode DLB 0 Digital loopback mode is disabled DLB 1 Digital loopback mode is enabled The receive signals including the receive frame sync signal are connected internally through multiplexers to the corresponding transmit signals SPCR1 12 11 CLKSTP Clock Stop Mode CLKSTP 0Xb Clock stop mode disab...

Page 130: ...tus 0 0 0 or 1 An external frame sync signal enters the McBSP through the FSR pin The signal is then inverted as determined by FSRP before being used as internal FSR Input 0 1 0 Internal FSR is driven by the sample rate generator frame sync signal FSG Output FSG is inverted as determined by FSRP before being driven out on the FSR pin 0 1 1 Internal FSR is driven by the sample rate generator frame ...

Page 131: ...he sample rate generator or driven by an external source The source of frame sync is selected by programming the mode bit FSRM in PCR FSR is also affected by the GSYNC bit in SRGR2 Similarly receive clocks can be selected to be inputs or outputs by programming the mode bit CLKRM in the PCR When FSR and FSX are inputs FSXM FSRM 0 external frame sync pulses the McBSP detects them on the internal fal...

Page 132: ...ing edge triggered clock before being sent to the transmitter If CLKXP 1 and internal clocking selected CLKXM 1 and CLKX is an output pin the internal rising edge triggered clock internal CLKX is inverted before being sent out on the CLKX pin Similarly the receiver can reliably sample data that is clocked with a rising edge clock by the transmitter The receive clock polarity bit CLKRP sets the edg...

Page 133: ...eceive Frame Sync Polarity Receiver Configuration 7 28 SPRU592E Figure 7 18 Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Data setup Data hold B7 B6 Internal CLKR DR ...

Page 134: ... 0000 SRGR1 15 8 7 0 FWID R W 0000 0000 Legend R Read W Write n Value after reset Table 7 22 Register Bits Used to Set the SRG Frame Sync Period and Pulse Width Register Bit Name Function SRGR2 11 0 FPER Sample Rate Generator Frame Sync Period For the frame sync signal FSG FPER 1 determines the period from the start of a frame sync pulse to the start of the next frame sync pulse Range for FPER 1 1...

Page 135: ...n the programmed word length The values in FPER and FWID are loaded into separate down counters The 12 bit FPER counter counts down the generated clock cycles from the programmed value 4095 maximum to 0 The 8 bit FWID counter counts down from the programmed value 255 maximum to 0 Figure 7 20 shows a frame sync period of 16 CLKG periods FPER 15 or 00001111b and a frame sync pulse with an active wid...

Page 136: ...plies the internal receive clock CLKR CLKRM 1 Internal CLKR is driven by the sample rate generator of the McBSP The CLKR pin is an output pin that reflects internal CLKR Case 2 Digital loopback mode set DLB 1 in SPCR1 CLKRM 0 The CLKR pin is in the high impedance state The internal receive clock CLKR is driven by the internal transmit clock CLKX Internal CLKX is derived according to the CLKXM bit ...

Page 137: ...internal receive clock signal CLKR and the internal receive frame synchronization signal FSR are internally connected to their transmit counterparts CLKX and FSX 7 19 1 Selecting a Source for the Receive Clock and a Data Direction for the CLKR Pin Table 7 24 shows how you can select various sources to provide the receive clock signal and the effect on the CLKR pin The polarity of the signal on the...

Page 138: ...rmined by CLKRP before being used Input 0 1 The sample rate generator clock CLKG drives internal CLKR Output CLKG inverted as determined by CLKRP is driven out on the CLKR pin 1 0 Internal CLKX drives internal CLKR For details on configuring CLKX see Chapter 8 Transmitter Configuration High impedance 1 1 Internal CLKX drives internal CLKR For details on configuring CLKX see Chapter 8 Transmitter C...

Page 139: ...When CLKR is configured as an output the internal CLKR is inverted before being driven on the CLKR pin The receive data is sampled on the rising edge of the external CLKR signal 7 20 1 About Frame Sync Pulses Clock Signals and Their Polarities Receive frame sync pulses can be either generated internally by the sample rate generator or driven by an external source The source of frame sync is select...

Page 140: ...l clocking is selected CLKXM 0 and CLKX is an input the external falling edge triggered input clock on CLKX is inverted to a rising edge triggered clock before being sent to the transmitter If CLKXP 1 and internal clocking selected CLKXM 1 and CLKX is an output pin the internal rising edge triggered clock internal CLKX is inverted before being sent out on the CLKX pin Similarly the receiver can re...

Page 141: ... Receive Clock Polarity Receiver Configuration 7 36 SPRU592E Figure 7 23 Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge Data setup Data hold B7 B6 Internal CLKR DR ...

Page 142: ...mple rate generator clock frequency The default value of CLKGDV is 1 divide input clock by 2 7 21 1 About the Sample Rate Generator Clock Divider The first divider stage generates the serial data bit clock from the input clock This divider stage utilizes a counter preloaded by CLKGDV that contains the divide ratio value The output of the first divider stage is the data bit clock which is output as...

Page 143: ...ncy of the slow peripheral clock see the TMS320VC5501 Fixed Point Digital Signal Processor Data Manual literature number SPRS206 or the TMS320VC5502 Fixed Point Digital Signal Processor Data Manual literature number SPRS166 Other timing limitations may also apply Refer to the device specific data manual for detailed information on the McBSP timing requirements When driving CLKX or CLKR at the pin ...

Page 144: ...rator Clock Synchronization GSYNC is used only when the input clock source for the sample rate generator is external on the CLKS or CLKR pin GSYNC 0 The sample rate generator clock CLKG is free running CLKG oscillates without adjustment and FSG pulses every FPER 1 CLKG cycles GSYNC 1 Clock synchronization is performed When a pulse is detected on the FSR pin CLKG is adjusted as necessary so that it...

Page 145: ...r Bits Used to Set the SRG Clock Mode Choose an Input Clock Register Bit Name Function PCR SRGR2 7 13 SCLKME CLKSM Sample Rate Generator Clock Mode SCLKME 0 CLKSM 0 Sample rate generator clock derived from CLKS pin SCLKME 0 CLKSM 1 Sample rate generator clock derived from McBSP internal input clock This is the condition forced by a DSP reset SCLKME 1 CLKSM 0 Sample rate generator clock derived fro...

Page 146: ...er Bits Used to Set the SRG Input Clock Polarity SRGR2 15 14 13 0 CLKSP R W 0 PCR 15 2 1 0 CLKXP CLKRP R W 0 R W 0 Legend R Read W Write n Value after reset Table 7 29 Register Bits Used to Set the SRG Input Clock Polarity Register Bit Name Function SRGR2 14 CLKSP CLKS Pin Polarity CLKSP determines the input clock polarity when the CLKS pin supplies the input clock SCLKME 0 and CLKSM 0 CLKSP 0 Ris...

Page 147: ... can produce a clock signal CLKG and a frame sync signal FSG for use by the receiver the transmitter or both To produce CLKG and FSG the sample rate generator must be driven by an input clock signal derived from the McBSP internal input clock or from an external clock on the CLKX pin CLKR pin or if present CLKS pin If you use a pin choose a polarity for the SRG input clock by programming the appro...

Page 148: ...rd Length s 8 11 8 10 Setting the Transmit Frame Length 8 13 8 11 Enabling Disabling the Transmit Frame Sync Ignore Function 8 15 8 12 Setting the Transmit Companding Mode 8 16 8 13 Setting the Transmit Data Delay 8 17 8 14 Setting the Transmit DXENA Mode 8 20 8 15 Setting the Transmit Interrupt Mode 8 21 8 16 Setting the Transmit Frame Sync Mode 8 22 8 17 Setting the Transmit Frame Sync Polarity ...

Page 149: ... 8 2 SPRU592E 8 1 Configuring the Transmitter To configure the McBSP transmitter perform the following procedure 1 Place the McBSP transmitter in reset 2 Program the McBSP registers for the desired transmitter operation 3 Take the transmitter out of reset ...

Page 150: ...gital loopback mode J Enable disable the clock stop mode J Enable disable transmit multichannel selection Data behavior J Choose one or two phases for the transmit frame J Set the transmit word length s J Set the transmit frame length J Enable disable the transmit frame sync ignore function J Set the transmit companding mode J Set the transmit data delay J Set the transmit DXENA mode J Set the tra...

Page 151: ...t state XRST 1 The serial port transmitter is enabled SPCR2 6 GRST Sample Rate Generator Reset GRST 0 Sample rate generator is reset If GRST 0 due to a DSP reset CLKG is driven by the McBSP internal input clock divided by 2 and FSG is driven low inactive If GRST 0 due to program code CLKG and FSG are both driven low inactive GRST 1 Sample rate generator is enabled CLKG is driven according to the c...

Page 152: ...tor can be reset directly by using the GRST bit in SPCR2 Table 8 2 shows the state of McBSP pins when the serial port is reset due to a DSP reset and a direct receiver transmitter reset Table 8 2 Reset State of Each McBSP Pin Pin Possible State s State Forced By DSP Reset State Forced By Receiver Transmitter Reset Receiver Reset RRST 0 and GRST 1 DR I Input Input CLKR I O Z Input Known state if In...

Page 153: ...d W Write n Value after reset Table 8 3 Register Bit Used to Set Transmitter Pins to Operate as McBSP Pins Register Bit Name Function PCR 13 XIOEN Transmit I O enable This bit is only applicable when the transmitter is in the reset state XRST 0 in SPCR2 XIOEN 0 The DX FSX CLKX and CLKS pins are configured as serial port pins and do not function as general purpose I Os XIOEN 1 The DX pin is a gener...

Page 154: ...15 DLB Digital Loopback Mode DLB 0 Digital loopback mode is disabled DLB 1 Digital loopback mode is enabled 8 5 1 About the Digital Loopback Mode In the digital loopback mode the receive signals are connected internally through multiplexers to the corresponding transmit signals as shown in Table 8 5 This mode allows testing of serial port code with a single DSP device the McBSP receives the data i...

Page 155: ... mode enabled with clock delay 8 6 1 About the Clock Stop Mode The clock stop mode supports the SPI master slave protocol If you are not using the SPI protocol you can clear CLKSTP to disable the clock stop mode In the clock stop mode the clock stops at the end of each data transfer At the beginning of each data transfer the clock starts immediately CLKSTP 10b or after a half cycle delay CLKSTP 11...

Page 156: ... can be disabled or masked XMCM 01b All channels are disabled unless they are selected in the appropriate transmit channel enable registers XCERs If enabled a channel in this mode is also unmasked The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs XMCM 10b All channels are enabled but they are masked unless they are selected in the appropriate transmit channel ena...

Page 157: ...o phases for the transmit frame Figure 8 6 Register Bit Used to Choose One or Two Phases for the Transmit Frame XCR2 15 14 0 XPHASE R W 0 Legend R Read W Write n Value after reset Table 8 8 Register Bit Used to Choose One or Two Phases for the Transmit Frame Register Bit Name Function XCR2 15 XPHASE Transmit phase number Specifies whether the transmit frame has one or two phases XPHASE 0 Single ph...

Page 158: ... W 000 Legend R Read W Write n Value after reset Table 8 9 Register Bits Used to Set the Transmit Word Length s Register Bit Name Function XCR1 7 5 XWDLEN1 Transmit Word Length of Frame Phase 1 XWDLEN1 000b 8 bits XWDLEN1 001b 12 bits XWDLEN1 010b 16 bits XWDLEN1 011b 20 bits XWDLEN1 100b 24 bits XWDLEN1 101b 32 bits XWDLEN1 11Xb Reserved XCR2 7 5 XWDLEN2 Transmit Word Length of Frame Phase 2 XWDL...

Page 159: ...ases depending on the value that you load into the XPHASE bit If a single phase frame is selected XWDLEN1 selects the length for every serial word transmitted in the frame If a dual phase frame is selected XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 determines the word length in phase 2 of the frame ...

Page 160: ...e after reset Table 8 10 Register Bits Used to Set the Transmit Frame Length Register Bit Name Function XCR1 14 8 XFRLEN1 Transmit frame length 1 XFRLEN1 1 is the number of serial words in phase 1 of the transmit frame XFRLEN1 000 0000 1 word in phase 1 XFRLEN1 000 0001 2 words in phase 1 XFRLEN1 111 1111 128 words in phase 1 XCR2 14 8 XFRLEN2 Transmit frame length 2 If a dual phase frame is selec...

Page 161: ...the length of phase 1 plus the length of phase 2 The 7 bit XFRLEN fields allow up to 128 words per phase See Table 8 11 for a summary of how to calculate the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization pulse Note Program the XFRLEN fields with w minus 1 where w represents the number of words per phase For the example if yo...

Page 162: ... Function XCR2 2 XFIG Transmit Frame Sync Ignore XFIG 0 An unexpected transmit frame sync pulse causes the McBSP to restart the frame transfer XFIG 1 The McBSP ignores unexpected transmit frame sync pulses 8 11 1 About Unexpected Frame Sync Pulses and the Frame Sync Ignore Function If a frame synchronization frame sync pulse starts the transfer of a new frame before the current frame is fully tran...

Page 163: ...00 Legend R Read W Write n Value after reset Table 8 13 Register Bits Used to Set the Transmit Companding Mode Register Bit Name Function XCR2 4 3 XCOMPAND Transmit Companding Mode Modes other than 00b are enabled only when the appropriate XWDLEN is 000b indicating 8 bit data XCOMPAND 00b No companding any size data MSB transmitted first XCOMPAND 01b No companding 8 bit data LSB transmitted first ...

Page 164: ...y XDATDLY 01 1 bit data delay XDATDLY 10 2 bit data delay XDATDLY 11 Reserved 8 13 1 About the Data Delay The start of a frame is defined by the first clock cycle in which frame synchronization is found to be active The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required This delay is called data delay XDATDLY specifies the data dela...

Page 165: ...edge of CLKR where an active high internal FSR is detected However data transmission must begin on the rising edge of the internal CLKX clock that generated the frame synchronization Therefore the first data bit is assumed to be present in XSR1 and thus on DX The transmitter then asynchronously detects the frame synchronization FSX going active high and immediately starts driving the first bit to ...

Page 166: ...Setting the Transmit Data Delay 8 19 Transmitter Configuration SPRU592E Figure 8 13 2 Bit Data Delay Used to Skip a Framing Bit DR Framing bit B5 B6 B7 FSR CLKR Á Á 2 bit delay ...

Page 167: ...r Mode DXENA 0 DX delay enabler is off DXENA 1 DX delay enabler is on 8 14 1 About the DXENA Mode The DXENA bit controls the delay enabler on the DX pin Set DXENA to enable an extra delay for turn on time for the length of the delay for a particular C55x device see the device specific data manual Note that this bit does not control the data itself so only the first bit is delayed If you tie togeth...

Page 168: ...e transmitter interrupt XINT signals the CPU of changes to the serial port status Four options exist for configuring this interrupt The options are set by the transmit interrupt mode bits XINTM in SPCR2 XINTM 00b Interrupt on every serial word by tracking the XRDY bit in SPCR2 Note that regardless of the value of XINTM XRDY can be read to detect the XRDY 1 condition XINTM 01b In any of the transmi...

Page 169: ...ce via the FSX pin FSXM 1 Transmit frame synchronization is supplied by the McBSP as determined by the FSGM bit of SRGR2 SRGR2 12 FSGM Sample Rate Generator Transmit Frame Synchronization Mode Used when FSXM 1 in PCR FSGM 0 The McBSP generates a transmit frame sync pulse when the content of DXR 1 2 is copied to XSR 1 2 FSGM 1 The transmitter uses frame sync pulses generated by the sample rate gene...

Page 170: ...SX pin 1 0 A DXR to XSR copy causes the McBSP to generate a transmit frame sync pulse that is 1 cycle wide Output The generated frame sync pulse is inverted as determined by FSXP before being driven out on FSX pin 8 16 2 Other Considerations If the sample rate generator creates a frame sync signal FSG that is derived from an external input clock the GSYNC bit determines whether FSG is kept synchro...

Page 171: ...rator or driven by an external source The source of frame sync is selected by programming the mode bit FSXM in PCR FSX is also affected by the FSGM bit in SRGR2 Similarly transmit clocks can be selected to be inputs or outputs by programming the mode bit CLKXM in the PCR When FSR and FSX are inputs FSXM FSRM 0 external frame sync pulses the McBSP detects them on the internal falling edge of clock ...

Page 172: ...ising edge triggered clock before being sent to the transmitter If CLKXP 1 and internal clocking selected CLKXM 1 and CLKX is an output pin the internal rising edge triggered clock internal CLKX is inverted before being sent out on the CLKX pin Similarly the receiver can reliably sample data that is clocked with a rising edge clock by the transmitter The receive clock polarity bit CLKRP sets the e...

Page 173: ...it Frame Sync Polarity Transmitter Configuration 8 26 SPRU592E Figure 8 19 Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge B6 B7 DR CLKR Data hold ÁÁ ÁÁ Data setup Internal ...

Page 174: ... pulse Range for FPER 1 1 to 4096 CLKG cycles SRGR1 15 8 FWID Sample Rate Generator Frame Sync Pulse Width This field plus 1 determines the width of each frame sync pulse on FSG Range for FWID 1 1 to 256 CLKG cycles 8 18 1 About the Frame Sync Period and the Frame Sync Pulse Width The sample rate generator can produce a clock signal CLKG and a frame sync signal FSG If the sample rate generator is ...

Page 175: ...pulse with an active width of 2 CLKG periods FWID 1 Figure 8 21 Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods FSG CLKG 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Frame sync period FPER 1 x CLKG Frame sync pulse width FWID 1 x CLKG When the sample rate generator comes out of reset FSG is in its inactive state Then when FRST 1 and FSGM 1 a frame sync pulse is generated The ...

Page 176: ... CLKX pin CLKXM 1 The CLKX pin is an output pin driven by the sample rate generator of the McBSP 8 19 1 Selecting a Source for the Transmit Clock and a Data Direction for the CLKX Pin Table 8 22 shows how the CLKXM bit selects the transmit clock and the corresponding status of the CLKX pin The polarity of the signal on the CLKX pin is determined by the CLKXP bit Table 8 22 How the CLKXM Bit Select...

Page 177: ...NC bit determines whether CLKG is kept synchronized with pulses on the FSR pin In the clock stop mode CLKSTP 10b or 11b the McBSP can act as a master or as a slave in the SPI protocol If the McBSP is a master make sure that CLKXM 1 so that CLKX is an output to supply the master clock to any slave devices If the McBSP is a slave make sure that CLKXM 0 so that CLKX is an input to accept the master c...

Page 178: ...e being used internally When CLKX is configured as an output the internal CLKX is not inverted before being driven on the CLKX pin The transmit data is driven on the falling edge of the external CLKX signal 8 20 1 About Frame Sync Pulses Clock Signals and Their Polarities Transmit frame sync pulses can be either generated internally by the sample rate generator or driven by an external source The ...

Page 179: ...nal clocking is selected CLKXM 0 and CLKX is an input the external falling edge triggered input clock on CLKX is inverted to a rising edge triggered clock before being sent to the transmitter If CLKXP 1 and internal clocking selected CLKXM 1 and CLKX is an output pin the internal rising edge triggered clock internal CLKX is inverted before being sent out on the CLKX pin Similarly the receiver can ...

Page 180: ...nsmit Clock Polarity 8 33 Transmitter Configuration SPRU592E Figure 8 24 Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge B6 B7 DR CLKR Data hold Á Á Data setup Internal ...

Page 181: ...e required sample rate generator clock frequency The default value of CLKGDV is 1 divide input clock by 2 8 21 1 About the Sample Rate Generator Clock Divider The first divider stage generates the serial data bit clock from the input clock This divider stage utilizes a counter preloaded by CLKGDV that contains the divide ratio value The output of the first divider stage is the data bit clock which...

Page 182: ...equency of the slow peripheral clock see the TMS320VC5501 Fixed Point Digital Signal Processor Data Manual literature number SPRS206 or the TMS320VC5502 Fixed Point Digital Signal Processor Data Manual literature number SPRS166 Other timing limitations may also apply See the device specific data manual for detailed information on the McBSP timing requirements When driving CLKX or CLKR at the pin c...

Page 183: ...erator Clock Synchronization GSYNC is used only when the input clock source for the sample rate generator is external on the CLKS or CLKR pin GSYNC 0 The sample rate generator clock CLKG is free running CLKG oscillates without adjustment and FSG pulses every FPER 1 CLKG cycles GSYNC 1 Clock synchronization is performed When a pulse is detected on the FSR pin CLKG is adjusted as necessary so that i...

Page 184: ...egister Bits Used to Set the SRG Clock Mode Choose an Input Clock Register Bit Name Function PCR SRGR2 7 13 SCLKME CLKSM Sample Rate Generator Clock Mode SCLKME 0 CLKSM 0 Sample rate generator clock derived from CLKS pin SCLKME 0 CLKSM 1 Sample rate generator clock derived from McBSP internal input clock This is the condition forced by a DSP reset SCLKME 1 CLKSM 0 Sample rate generator clock deriv...

Page 185: ...ster Bits Used to Set the SRG Input Clock Polarity SRGR2 15 14 13 0 CLKSP R W 0 PCR 15 2 1 0 CLKXP CLKRP R W 0 R W 0 Legend R Read W Write n Value after reset Table 8 27 Register Bits Used to Set the SRG Input Clock Polarity Register Bit Name Function SRGR2 14 CLKSP CLKS Pin Polarity CLKSP determines the input clock polarity when the CLKS pin supplies the input clock SCLKME 0 and CLKSM 0 CLKSP 0 R...

Page 186: ...r can produce a clock signal CLKG and a frame sync signal FSG for use by the receiver the transmitter or both To produce CLKG and FSG the sample rate generator must be driven by an input clock signal derived from the McBSP internal input clock or from an external clock on the CLKX pin CLKR pin or if present CLKS pin If you use a pin choose a polarity for the SRG input clock by programming the appr...

Page 187: ...Transmitter Configuration 8 40 SPRU592E This page is intentionally left blank ...

Page 188: ...9 1 General Purpose I O on the McBSP Pins This chapter summarizes how to use the McBSP pins as general purpose I O GPIO pins Topic Page 9 1 Using the McBSP Pins for GPIO 9 2 Chapter 9 ...

Page 189: ...Table 9 1 shows which bits in PCR are used to read from write to these pins For the transmitter pins CLKX FSX and DX you must meet two similar conditions The transmitter of the serial port is in reset XRST 0 in SPCR2 General purpose I O is enabled for the serial port transmitter XIOEN 1 in PCR The CLKX and FSX pins can be individually configured as input or output pins with the CLKXM and FSXM bits...

Page 190: ...RRST 0 RIOEN 1 FSRM 1 FSRP FSRM 0 FSRP DR RRST 0 RIOEN 1 Never Does not apply Always DRSTAT CLKS RRST XRST 0 RIOEN XIOEN 1 Never Does not apply Always CLKSSTAT Note When the McBSP pins are configured as general purpose input pins CLKRP CLKXP CLKSP FSRP and FSXP are not write protected If written they contain the written value until they are next automatically updated with the state of the associat...

Page 191: ...General Purpose I O on the McBSP Pins 9 4 SPRU592E This page is intentionally left blank ...

Page 192: ...conserve power in the DSP by placing the McBSP into its idle mode How to reset and initialize the various parts of the McBSP Topic Page 10 1 McBSP Emulation Mode 10 2 10 2 McBSP Power Management on the TMS320VC5503 5507 5509 and TMS320VC5510 Devices 10 3 10 3 McBSP Power Management on the TMS320VC5501 and TMS320VC5502 Devices 10 4 10 4 Resetting and Initializing a McBSP 10 5 Chapter 10 ...

Page 193: ...hese options are listed in Table 10 1 The McBSP receiver responds to an emulation suspend event in a similar fashion Note that if the receiver continues to run but the DMA controller is stopped an overrun error is possible In such a case an interrupt service routine should be in place to read the data receive registers to restart the McBSP receiver or to reset the McBSP receiver Table 10 1 McBSP E...

Page 194: ...nd frame synchronization it will be completely stopped If the McBSP is configured to operate with externally generated clocking and frame synchronization either directly or through the sample rate generator the external interface portion of the McBSP continues to function during periods of external clock activity The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs t...

Page 195: ...ates RRST 0 in SPCR1 and XRST 0 in SPCR2 In the McBSP idle mode If the McBSP is configured to operate with internally generated clocking and frame synchronization it will be completely stopped If the McBSP is configured to operate with externally generated clocking and frame synchronization either directly or through the sample rate generator the external interface portion of the McBSP continues t...

Page 196: ...inactive state if output CLKS I Input Input Note In Possible State s column I Input O Output Z High impedance 10 4 2 DSP Reset McBSP Reset and Sample Rate Generator Reset When a DSP reset or a McBSP reset occurs the McBSP is reset to its initial state including reset of all counters and status bits The receive status bits include RFULL RRDY and RSYNCERR The transmit status bits include XEMPTY XRDY...

Page 197: ... are in an inactive state when RRST 0 and XRST 0 respectively even if they are outputs driven by FSG This ensures that when only one portion of the McBSP is in reset the other portion can continue operation when FRST 1 and its frame synchronization is driven by FSG Sample rate generator reset The sample rate generator is reset when the DSP is reset or when GRST is loaded with 0 In the case of a DS...

Page 198: ...the desired bit The above procedure for reset initialization can be applied in general when the receiver or transmitter has to be reset during its normal operation and also when the sample rate generator is not used for either operation Notes 1 The necessary duration of the active low period of XRST or RRST is at least two CLKR CLKX cycles 2 The appropriate bits in serial port configuration regist...

Page 199: ...ansmit clock is driven by an external source Receive frame synchronization continues to be driven by an external source The receive clock continues to be driven by the sample rate generator The input clock of the sample rate generator is supplied by the CLKS pin or by the McBSP internal input clock depending on the CLKSM bit of SRGR2 SRGR1 0001h SRGR2 2000h The McBSP internal input clock is the in...

Page 200: ...xternally by another source In a multichannel mode configuration with external frame sync generation the TMS320VC5501 02 McBSP transmitter will ignore the first frame sync pulse after it is taken out of reset The transmitter will transmit only on the second frame sync pulse The receiver will shift in data on the first frame sync pulse regardless of whether it is generated internally or externally ...

Page 201: ...Emulation Power and Reset Considerations 10 10 SPRU592E ...

Page 202: ...This chapter shows two ways you can implement data packing with the McBSP Topic Page 11 1 Data Packing Using Frame Length and Word Length 11 2 11 2 Data Packing Using Word Length and the Frame Sync Ignore Function 11 4 Chapter 11 ...

Page 203: ... bit data words are transferred to and from the McBSP by the CPU or by the DMA controller Thus four reads from DRR1 and four writes to DXR1 are necessary for each frame Figure 11 1 Four 8 Bit Data Words Transferred To From the McBSP RSR1 to RBR1 copy RBR1 copy RSR1 to RSR1 to RBR1 copy RBR1 copy RSR1 to DXR1 to XSR1 copy DXR1 to XSR1 copy DXR1 to XSR1 copy DXR1 to XSR1 copy Word 1 Word 2 Word 3 Wo...

Page 204: ...t Note When the word length is larger than 16 bits make sure you access DRR2 DXR2 before you access DRR1 DXR1 McBSP activity is tied to accesses of DRR1 DXR1 During the reception of 24 bit or 32 bit words read DRR2 and then read DRR1 Otherwise the next RBR 1 2 to DRR 1 2 copy occurs before DRR2 is read Similarly during the transmission of 24 bit or 32 bit words write to DXR2 and then write to DXR1...

Page 205: ...tion requires one read operation for each word For transmission this configuration requires one write operation for each word Figure 11 3 8 Bit Data Words Transferred at Maximum Packet Frequency RBR1 to DRR1 copy DRR1 copy RBR1 to RBR1 to DRR1 copy DRR1 copy RBR1 to DXR1 to XSR1 copy DXR1 to XSR1 copy DXR1 to XSR1 copy DXR1 to XSR1 copy Word 1 Word 2 Word 3 Word 4 CLKR FSR DR CLKX FSX DX Figure 11...

Page 206: ... to XSR2 copy DXR1 to XSR1 copy Word 1 CLKR FSR DR CLKX FSX DX Frame ignored Frame ignored Frame ignored Frame ignored Frame ignored Frame ignored Note On the TMS320VC5501 and TMS320VC5502 devices if a 0 bit delay and an external clock are used the transfer shown in Figure 11 3 can only be achieved if the frame sync ignore bit is set to 1 If the frame sync ignore bit is 0 an additional clock cycle...

Page 207: ...Data Packing Examples 11 6 SPRU592E This page is intentionally left blank ...

Page 208: ...ers DXR1 and DXR2 12 3 12 3 Serial Port Control Registers SPCR1 and SPCR2 12 4 12 4 Receive Control Registers RCR1 and RCR2 12 13 12 5 Transmit Control Registers XCR1 and XCR2 12 19 12 6 Sample Rate Generator Registers SRGR1 and SRGR2 12 25 12 7 Multichannel Control Registers MCR1 and MCR2 12 31 12 8 Pin Control Register PCR 12 38 12 9 Receive Channel Enable Registers RCERA RCERH 12 46 12 10 Trans...

Page 209: ... Value after reset 12 1 1 How Data Travels From the Data Receive DR Pin to the DRRs If the serial word length is 16 bits or smaller receive data on the DR pin is shifted into receive shift register 1 RSR1 and then copied into receive buffer register 1 RBR1 The content of RBR1 is then copied to DRR1 which can be read by the CPU or by the DMA controller If the serial word length is larger than 16 bi...

Page 210: ...15 0 Transmit data for 8 12 or 16 bit data or Low part of receive data for 20 24 or 32 bit data R W 0 Legend R Read W Write n Value after reset 12 2 1 How Data Travels From the DXRs to the Data Transmit DX Pin If the serial word length is 16 bits or fewer data written to DXR1 is copied to transmit shift register 1 XSR1 From XSR1 the data is shifted onto the DX pin one bit at a time If the serial w...

Page 211: ...nd XINTM emulation mode FREE and SOFT Turn on and off the DX pin delay enabler DXENA Check the status of receive and transmit operations RSYNCERR XSYNCERR RFULL XEMPTY RRDY XRDY Reset portions of the McBSP RRST XRST FRST GRST Figure 12 3 Serial Port Control Registers SPCR1 and SPCR2 SPCR1 15 14 13 12 11 10 8 DLB RJUST CLKSTP Reserved R W 0 R W 00 R W 00 R 0 7 6 5 4 3 2 1 0 DXENA Reserved RINTM RSY...

Page 212: ... are supplied by their respective pins or are generated internally depending on the mode bits FSXM and CLKXM This mode allows you to test serial port code with a single DSP The McBSP transmitter directly supplies data frame synchronization and clocking to the McBSP receiver 14 13 RJUST Receive sign extension and justification mode bits During reception RJUST determines how data is justified and bi...

Page 213: ...fer At the beginning of each data transfer the clock starts immediately CLKSTP 10b or after a half cycle delay CLKSTP 11b 00b or 01b Clock stop mode is disabled 10b Clock stop mode without clock delay 11b Clock stop mode with half cycle clock delay 10 8 Reserved These read only reserved bits return 0s when read 7 DXENA DX delay enabler mode bit DXENA controls the delay enabler for the DX pin The e...

Page 214: ...BSP sends a RINT request to the CPU when each receive frame sync pulse is detected The interrupt request is sent even if the receiver is in its reset state 11b The McBSP sends a RINT request to the CPU when the RSYNCERR bit is set indicating a receive frame sync error Note Regardless of the value of RINTM you can check RSYNCERR to determine whether a receive frame sync error occurred 3 RSYNCERR Re...

Page 215: ...eady When the content of DRR1 is read RRDY is automatically cleared 1 Receiver ready New data can be read from DRR 1 2 Important If both DRRs are needed word length larger than 16 bits the CPU or the DMA controller must read from DRR2 first and then from DRR1 As soon as DRR1 is read the next RBR to DRR copy is initiated If DRR2 is not read first the data in DRR2 is lost 0 RRST Receiver reset bit Y...

Page 216: ... 1 Free run The McBSP transmit and receive clocks continue to run 8 SOFT Soft stop bit When FREE 0 SOFT determines the response of the McBSP transmit and receive clocks when an emulation suspend event such as a breakpoint occurs When one of the clocks stops the corresponding data transfer transmission or reception stops 0 Hard stop The McBSP transmit and receive clocks are stopped immediately 1 So...

Page 217: ...ample rate generator as a whole is enabled GRST 1 the frame sync logic generates the frame sync signal FSG as programmed 6 GRST Sample rate generator reset bit You can use GRST to take the McBSP sample rate generator into and out of its reset state Note This bit has a negative polarity GRST 0 indicates the reset state 0 If you read a 0 the sample rate generator is in its reset state If you write a...

Page 218: ...he CPU after every 16 channel block is transmitted in a frame Outside of the multichannel selection mode no interrupt request is sent 10b The McBSP sends an XINT request to the CPU when each transmit frame sync pulse is detected The interrupt request is sent even if the transmitter is in its reset state 11b The McBSP sends an XINT request to the CPU when the XSYNCERR bit is set indicating a transm...

Page 219: ...s a transmit interrupt XINT request to the CPU when XRDY changes from 0 to 1 Also when XRDY changes from 0 to 1 the McBSP sends a transmit synchronization event XEVT signal to the DMA controller 0 Transmitter not ready When DXR1 is loaded XRDY is automatically cleared 1 Transmitter ready DXR 1 2 is ready to accept new data Important If both DXRs are needed word length larger than 16 bits the CPU o...

Page 220: ...ASE Define two parameters for phase 1 and if necessary phase 2 the serial word length RWDLEN1 RWDLEN2 and the number of words RFRLEN1 RFRLEN2 Choose a receive companding mode if any RCOMPAND Enable or disable the receive frame sync ignore function RFIG Choose a receive data delay RDATDLY Figure 12 4 Receive Control Registers RCR1 and RCR2 RCR1 15 14 8 Reserved RFRLEN1 R 0 R W 0 7 5 4 0 RWDLEN1 Res...

Page 221: ...frame is selected RFRLEN1 determines the number of serial words in phase 1 of the frame and RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame The 7 bit RFRLEN fields allow up to 128 words per phase See the following table for a summary of how you determine the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronizatio...

Page 222: ...a single phase frame is selected RWDLEN1 in RCR1 selects the length for every serial word received in the frame If a dual phase frame is selected RWDLEN1 determines the length of the serial words in phase 1 of the frame and RWDLEN2 in RCR2 determines the word length in phase 2 of the frame 000b 8 bits 001b 12 bits 010b 16 bits 011b 20 bits 100b 24 bits 101b 32 bits other Reserved do not use 4 0 Re...

Page 223: ...have one or two phases depending on value that you load into the RPHASE bit If a single phase frame is selected RFRLEN1 in RCR1 selects the number of serial words in the frame If a dual phase frame is selected RFRLEN1 determines the number of serial words in phase 1 of the frame and RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame The 7 bit RFRLEN fields allow up to 128 words...

Page 224: ...gth of the serial words in phase 1 of the frame and RWDLEN2 in RCR2 determines the word length in phase 2 of the frame 000b 8 bits 001b 12 bits 010b 16 bits 011b 20 bits 100b 24 bits 101b 32 bits other Reserved do not use 4 3 RCOMPAND Receive companding mode bits Companding COMpress and exPAND hardware allows compression and expansion of data in either µ law or A law format RCOMPAND allows you to ...

Page 225: ...g reception 0 Frame sync detect An unexpected FSR pulse causes the receiver to discard the contents of RSR 1 2 in favor of the new incoming data The receiver 1 Aborts the current data transfer 2 Sets RSYNCERR in SPCR1 3 Begins the transfer of a new data word 1 Frame sync ignore An unexpected FSR pulse is ignored Reception continues uninterrupted 1 0 RDATDLY Receive data delay bits RDATDLY specifie...

Page 226: ...ASE Define two parameters for phase 1 and if necessary phase 2 the serial word length XWDLEN1 XWDLEN2 and the number of words XFRLEN1 XFRLEN2 Choose a transmit companding mode if any XCOMPAND Enable or disable the transmit frame sync ignore function XFIG Choose a transmit data delay XDATDLY Figure 12 5 Transmit Control Registers XCR1 and XCR2 XCR1 15 14 8 Reserved XFRLEN1 R 0 R W 0 7 5 4 0 XWDLEN1...

Page 227: ...rame is selected XFRLEN1 determines the number of serial words in phase 1 of the frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame The 7 bit XFRLEN fields allow up to 128 words per phase See the following table for a summary of how you determine the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization...

Page 228: ...ingle phase frame is selected XWDLEN1 in XCR1 selects the length for every serial word transmitted in the frame If a dual phase frame is selected XWDLEN1 determines the length of the serial words in phase 1 of the frame and XWDLEN2 in XCR2 determines the word length in phase 2 of the frame 000b 8 bits 001b 12 bits 010b 16 bits 011b 20 bits 100b 24 bits 101b 32 bits other Reserved do not use 4 0 Re...

Page 229: ... have one or two phases depending on value that you load into the XPHASE bit If a single phase frame is selected XFRLEN1 in XCR1 selects the number of serial words in the frame If a dual phase frame is selected XFRLEN1 determines the number of serial words in phase 1 of the frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame The 7 bit XFRLEN fields allow up to 128 word...

Page 230: ...the serial words in phase 1 of the frame and XWDLEN2 in XCR2 determines the word length in phase 2 of the frame 000b 8 bits 001b 12 bits 010b 16 bits 011b 20 bits 100b 24 bits 101b 32 bits other Reserved do not use 4 3 XCOMPAND Transmit companding mode bits Companding COMpress and exPAND hardware allows compression and expansion of data in either µ law or A law format XCOMPAND allows you to choose...

Page 231: ...es the transmitter to discard the content of XSR 1 2 The transmitter 1 Aborts the present transmission 2 Sets XSYNCERR in SPCR2 3 Begins a new transmission from DXR 1 2 If new data was written to DXR 1 2 since the last DXR 1 2 to XSR 1 2 copy the current value in XSR 1 2 is lost Otherwise the same data is transmitted 1 Frame sync ignore An unexpected FSX pulse is ignored Transmission continues uni...

Page 232: ... FWID and specify the period between those pulses FPER When an external source via the CLKS CLKR or CLKX pin provides the input clock source for the sample rate generator If the CLKS pin provides the input clock the CLKSP bit in SRGR2 allows you to select whether the rising edge or the falling edge of CLKS triggers CLKG and FSG If the CLKX CLKR pin is used instead of the CLKS pin the polarity of t...

Page 233: ... 5507 5509 and TMS320VC5510 devices bit 14 provides the GSYNC function described in Table 12 8 On C55x devices that do not have a CLKS pin bit 14 is a don t care Table 12 7 SRGR1 Bit Descriptions Bit Field Value Description 15 8 FWID 0 255 Frame sync pulse width bits for FSG The sample rate generator can produce a clock signal CLKG and a frame sync signal FSG For frame sync pulses on FSG FWID 1 is...

Page 234: ... and CLKSM bits SCLKME CLKSM Input Clock For Sample Rate Generator 0 0 Signal on CLKS pin 0 1 McBSP internal input clock 1 0 Signal on CLKR pin 1 1 Signal on CLKX pin A DSP reset forces the CLKG frequency to 1 2 the input clock frequency CLKGDV 1 and the reset selects the McBSP internal input clock as the input clock The maximum frequency for the McBSP on the TMS320VC5503 5507 5509 and TMS320VC551...

Page 235: ...available and this is a reserved bit Always write 0 to this bit 0 No clock synchronization CLKG oscillates without adjustment and FSG pulses every FPER 1 CLKG cycles 1 Clock synchronization CLKG is adjusted as necessary so that it is synchronized with the input clock on the CLKS or CLKR pin FSG pulses FSG only pulses in response to a pulse on the FSR pin The frame sync period defined in FPER is ig...

Page 236: ...the source for the input clock A DSP reset selects the McBSP internal input clock as the input clock and forces the CLKG frequency to 1 2 the McBSP internal input clock frequency 0 The input clock for the sample rate generator is taken from the CLKS pin or from the CLKR pin depending on the value of the SCLKME bit of PCR SCLKME CLKSM Input Clock For Sample Rate Generator 0 0 Signal on CLKS pin 1 0...

Page 237: ...t frame sync pulse when the content of DXR 1 2 is copied to XSR 1 2 1 If FSXM 1 the transmitter uses frame sync pulses generated by the sample rate generator Program the FWID bits to set the width of each pulse Program the FPER bits to set the period between pulses 11 0 FPER 0 4095 Frame sync period bits for FSG The sample rate generator can produce a clock signal CLKG and a frame sync signal FSG ...

Page 238: ... and masked unmasked for transmission XMCM Specify whether two partitions 32 channels at a time or eight partitions 128 channels at a time can be used RMCME for reception XMCME for transmission Assign blocks of 16 channels to partitions A and B when the 2 partition mode is selected RPABLK and RPBBLK for reception XPABLK and XPBBLK for transmission Determine which block of 16 channels is currently ...

Page 239: ...o 32 channels in the receive multichannel selection mode RMCM 1 Assign 16 channels to partition A with the RPABLK bits Assign 16 channels to partition B with the RPBBLK bits You control the channels with the appropriate receive channel enable registers RCERA Channels in partition A RCERB Channels in partition B 1 8 partition mode All partitions A through H are used You can control up to 128 channe...

Page 240: ...ndling activity in the other partition For example while the block in partition A is active you can change which block is assigned to partition B The RCBLK bits are regularly updated to indicate which block is active Note When XMCM 11b for symmetric transmission and reception the transmitter uses the receive block bits RPABLK and RPBBLK rather than the transmit block bits XPABLK and XPBBLK 00b Blo...

Page 241: ...els 80 through 95 110b Block 6 channels 96 through 111 111b Block 7 channels 112 through 127 1 Reserved 0 Reserved bits not available for your use They are read only bits and return 0s when read 0 RMCM Receive multichannel selection mode bit RMCM determines whether all channels or only selected channels are enabled for reception 0 All 128 channels are enabled 1 Multichannel selection mode Channels...

Page 242: ...n 16 channels to partition A with the XPABLK bits Assign 16 channels to partition B with the XPBBLK bits If XMCM 11b for symmetric transmission and reception assign 16 channels to receive partition A with the RPABLK bits Assign 16 channels to receive partition B with the RPBBLK bits You control the channels with the appropriate transmit channel enable registers XCERA Channels in partition A XCERB ...

Page 243: ... transmitter is handling activity in the other partition For example while the block in partition A is active you can change which block is assigned to partition B The XCBLK bits are regularly updated to indicate which block is active Note When XMCM 11b for symmetric transmission and reception the transmitter uses the receive block bits RPABLK and RPBBLK rather than the transmit block bits XPABLK ...

Page 244: ...s off All channels are enabled and unmasked No channels can be disabled or masked 01b All channels are disabled unless they are selected in the appropriate transmit channel enable registers XCERs If enabled a channel in this mode is also unmasked The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs 10b All channels are enabled but they are masked unless they are sel...

Page 245: ...rature number SPRS206 for the TMS320VC5502 implementation see the TMS320VC5502 Fixed Point Digital Signal Processor Data Manual literature number SPRS166 Specify whether McBSP pins can be used as general purpose I O pins when the transmitter and or receiver is in its reset state XIOEN and RIOEN Choose a frame sync mode for the transmitter FSXM and for the receiver FSRM Choose a clock mode for tran...

Page 246: ... PERIPH idle domain is configured to be idle and IDLEEN 1 the McBSP stops and enters a low power state On the TMS320VC5501 and TMS320VC5502 devices This bit is reserved and should be written as 0 The IDLEEN function is implemented in the Peripheral Idle Control Register PICR For more information on the PICR see the TMS320VC5501 Fixed Point Digital Signal Processor Data Manual literature number SPR...

Page 247: ... CLKR FSR DR and CLKS pins are serial port pins 1 If RRST 0 the CLKR FSR and DR pins are GPIO pins The CLKS is also a GPIO pin if XRST 0 and XIOEN 1 Pin General Purpose Use Enabled by This Bit Combination Selected as Output When Output Value Driven From This Bit Selected As Input When Input Value Read From This Bit CLKX XRST 0 XIOEN 1 CLKXM 1 CLKXP CLKXM 0 CLKXP FSX XRST 0 XIOEN 1 FSXM 1 FSXP FSXM...

Page 248: ...plied by an external source via the FSX pin 1 Transmit frame synchronization is supplied by the McBSP as determined by the FSGM bit of SRGR2 10 FSRM Receive frame sync mode bit FSRM determines whether receive frame sync pulses are supplied externally or internally The polarity of the signal on the FSR pin is determined by the FSRP bit 0 Receive frame synchronization is supplied by an external sour...

Page 249: ...lock signal from an external source via the CLKX pin 1 Internal CLKX is driven by the sample rate generator of the McBSP The CLKX pin is an output pin that reflects internal CLKX In clock stop mode CLKSTP 10b or 11b 0 The McBSP is a slave in the SPI protocol The internal transmit clock CLKX is driven by the SPI master via the CLKX pin The internal receive clock CLKR is driven internally by CLKX so...

Page 250: ...igital loopback mode DLB 0 0 The CLKR pin is an input pin that supplies the internal receive clock CLKR 1 Internal CLKR is driven by the sample rate generator of the McBSP The CLKR pin is an output pin that reflects internal CLKR In digital loopback mode DLB 1 0 The CLKR pin is in the high impedance state The internal receive clock CLKR is driven by the internal transmit clock CLKX CLKX is derived...

Page 251: ...e sample rate generator is taken from the CLKR pin or from the CLKX pin depending on the value of the CLKSM bit of SRGR2 SCLKME CLKSM Input Clock For Sample Rate Generator 1 0 Signal on CLKR pin 1 1 Signal on CLKX pin 6 CLKSSTAT CLKS pin status bit When CLKSSTAT is applicable it reflects the level on the CLKS pin CLKSSTAT is only applicable when the transmitter and receiver are both in reset XRST ...

Page 252: ...larity of CLKX as seen on the CLKX pin This bit also can effect the sample rate generator see section 3 1 on page 3 2 and effects the clock stop mode see Chapter 6 0 Transmit data is driven on the rising edge of CLKX 1 Transmit data is driven on the falling edge of CLKX 0 CLKRP Receive clock polarity bit CLKRP determines the polarity of CLKR as seen on the CLKR pin This bit also can effect the sam...

Page 253: ...individual enabling and disabling of the channels RMCM 1 Figure 12 9 Format of the Receive Channel Enable Registers RCERA RCERH 15 14 13 12 11 10 9 8 RCE15 RCE14 RCE13 RCE12 RCE11 RCE10 RCE9 RCE8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 RCE7 RCE6 RCE5 RCE4 RCE3 RCE2 RCE1 RCE0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read W Write n Value after reset Table 12 1...

Page 254: ...ber of S l t bl Block Assignments Channel Assignments Selectable Channels RCERx Block Assigned Bit in RCERx Channel Assigned 32 RMCME 0 RCERA Channels n to n 15 The block of channels is chosen with the RPABLK bits RCE0 RCE1 RCE2 RCE15 Channel n Channel n 1 Channel n 2 Channel n 15 RCERB Channels m to m 15 The block of channels is chosen with the RPBBLK bits RCE0 RCE1 RCE2 RCE15 Channel m Channel m...

Page 255: ...ents Number of Selectable Channels Channel Assigned Bit in RCERx Block Assigned RCERx RCERE Block 4 RCE0 RCE1 RCE2 RCE15 Channel 64 Channel 65 Channel 66 Channel 79 RCERF Block 5 RCE0 RCE1 RCE2 RCE15 Channel 80 Channel 81 Channel 82 Channel 95 RCERG Block 6 RCE0 RCE1 RCE2 RCE15 Channel 96 Channel 97 Channel 98 Channel 111 RCERH Block 7 RCE0 RCE1 RCE2 RCE15 Channel 112 Channel 113 Channel 114 Chann...

Page 256: ...ach bit XCEx of a transmit channel enable register The I O mapped XCERs are only used when the transmitter is configured to allow individual disabling enabling and masking unmasking of the channels XMCM is nonzero Figure 12 10 Format of the Transmit Channel Enable Registers XCERA XCERH 15 14 13 12 11 10 9 8 XCE15 XCE14 XCE13 XCE12 XCE11 XCE10 XCE9 XCE8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W...

Page 257: ...less selected 0 Mask the channel that is mapped to XCEx Even if the channel is enabled by the corresponding receive channel enable bit this channel s data cannot appear on the DX pin 1 Unmask the channel that is mapped to XCEx If the channel is also enabled by the corresponding receive channel enable bit full transmission can occur 12 10 1 XCERs Used in a Transmit Multichannel Selection Mode For m...

Page 258: ...chosen with the RPABLK bits XCE0 XCE1 XCE2 XCE15 Channel n Channel n 1 Channel n 2 Channel n 15 XCERB Channels m to m 15 When XMCM 01b or 10b the block of channels is chosen with the XPBBLK bits When XMCM 11b the block is chosen with the RPBBLK bits XCE0 XCE1 XCE2 XCE15 Channel m Channel m 1 Channel m 2 Channel m 15 128 XMCME 1 XCERA Block 0 XCE0 XCE1 XCE2 XCE15 Channel 0 Channel 1 Channel 2 Chann...

Page 259: ...ignments Block Assignments Number of Selectable Channels Channel Assigned Bit in XCERx Block Assigned XCERx XCERE Block 4 XCE0 XCE1 XCE2 XCE15 Channel 64 Channel 65 Channel 66 Channel 79 XCERF Block 5 XCE0 XCE1 XCE2 XCE15 Channel 80 Channel 81 Channel 82 Channel 95 XCERG Block 6 XCE0 XCE1 XCE2 XCE15 Channel 96 Channel 97 Channel 98 Channel 111 XCERH Block 7 XCE0 XCE1 XCE2 XCE15 Channel 112 Channel...

Page 260: ...very register field for entering the binary value that needs to be loaded into that field When all of the fields have been filled in you can use the line above the register figure to record the corresponding hexadecimal value to load into the register during initialization Topic Page 13 1 General Control Registers 13 2 13 2 Multichannel Selection Control Registers 13 5 Chapter 13 ...

Page 261: ...RST Á Á ÁÁ ÁÁ ÁÁ ÁÁ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁÁ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Read only ÁÁÁÁ ÁÁÁÁ Read only ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPCR2 Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ...

Page 262: ...ÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Read onlyÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Read only ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ On the TMS320VC5501 and TMS320VC5502 devices this bit is reserved and should be written with 0 Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCR1 Initialization Value ____________________________________________________________ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ...

Page 263: ... Á Á ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SRGR1 Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 15 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 7 0 Á ÁÁ ÁÁ ÁÁ Î...

Page 264: ...Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERA Initialization Value ___________________________________________________________ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 14 ÁÁÁÁ ÁÁÁÁ 13 ÁÁÁÁÁ ÁÁÁÁÁ 12 ÁÁÁÁ ÁÁÁÁ 11 ÁÁÁÁ ÁÁÁÁ 10 ÁÁÁÁÁ ÁÁÁÁÁ 9 ÁÁÁÁ ÁÁÁÁ 8 ÁÁ ÁÁ ÁÁ ÁÁ Á Á RCE15 ÎÎÎÎÎ ÎÎÎÎÎ RCE14 ÎÎÎÎ ÎÎÎÎ RCE13ÎÎÎÎÎ ...

Page 265: ...Á ÁÁÁÁ Channel _________ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel _________ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel _________ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel _________ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel _________ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERC Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á...

Page 266: ...Á ÁÁÁÁ ÁÁÁÁ Channel 51 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 50 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel 49 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 48 ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERE Initialization Value ___________________________________________________________ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 14 ÁÁÁÁ ÁÁÁÁ 13 ÁÁÁÁÁ ÁÁÁÁÁ 12 ...

Page 267: ...ÁÁ ÁÁÁÁÁ Channel 83 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 82 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 81 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel 80 Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERG Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁ ÁÁÁÁ 14 ÁÁÁÁÁ ÁÁÁÁÁ 13 ÁÁÁÁ ÁÁÁÁ 12 ÁÁÁÁ Á...

Page 268: ...ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel 113 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 112 ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERA Initialization Value ___________________________________________________________ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 14 ÁÁÁÁ ÁÁÁÁ 13 ÁÁÁÁÁ ÁÁÁÁÁ 12 ÁÁÁÁ ÁÁÁÁ 11 ÁÁÁÁ ÁÁÁÁ 10 ÁÁÁÁÁ ÁÁÁÁÁ 9 ÁÁÁÁ ÁÁÁ...

Page 269: ...ÁÁ ÁÁÁÁ Channel _________ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel _________ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel _________ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel _________ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel _________ Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERC Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ...

Page 270: ...ÁÁ ÁÁÁÁ ÁÁÁÁ Channel 51 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 50 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel 49 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 48 ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERE Initialization Value ___________________________________________________________ ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 14 ÁÁÁÁ ÁÁÁÁ 13 ÁÁÁÁÁ ÁÁÁÁÁ 12...

Page 271: ...ÁÁÁ ÁÁÁÁÁ Channel 83 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 82 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Channel 81 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Channel 80 Á Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERG Initialization Value ___________________________________________________________ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ 15 ÁÁÁÁ ÁÁÁÁ 14 ÁÁÁÁÁ ÁÁÁÁÁ 13 ÁÁÁÁ ÁÁÁÁ 12 ÁÁÁÁ ...

Page 272: ... ÁÁÁÁ ÁÁÁÁ Channel 127 ÁÁÁÁÁ ÁÁÁÁÁ Channel 126 ÁÁÁÁ ÁÁÁÁ Channel 125 ÁÁÁÁÁ ÁÁÁÁÁ Channel 124 ÁÁÁÁ ÁÁÁÁ Channel 123 ÁÁÁÁ ÁÁÁÁ Channel 122 ÁÁÁÁÁ ÁÁÁÁÁ Channel 121 ÁÁÁÁ ÁÁÁÁ Channel 120 ÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 7 ÁÁÁÁ ÁÁÁÁ 6 ÁÁÁÁ ÁÁÁÁ 5 ÁÁÁÁÁ ÁÁÁÁÁ 4 ÁÁÁÁ ÁÁÁÁ 3 ÁÁÁÁ ÁÁÁÁ 2 ÁÁÁÁÁ ÁÁÁÁÁ 1 ÁÁÁ...

Page 273: ...McBSP Register Worksheet 13 14 SPRU592E This page is intentionally left blank ...

Page 274: ...changes made since the previous version of the document Table A 1 Document Revision History Page Additions Modifications Deletions 2 10 Changed the second note on page 2 10 2 14 Changed the note on page 2 14 11 5 Changed the note on page 11 5 Appendix A ...

Page 275: ...n table 12 43 shown in figure 12 39 CLKRP bit of PCR described in table 12 45 shown in figure 12 39 CLKS pin 1 6 CLKS pin polarity bit CLKSP described in table 12 28 shown in figure 12 26 CLKS pin status bit CLKSSTAT described in table 12 44 shown in figure 12 39 CLKSM bit of SRGR2 described in table 12 29 shown in figure 12 26 CLKSP bit of SRGR2 described in table 12 28 shown in figure 12 26 CLKS...

Page 276: ...2 data direction for CLKX pin 8 29 data packing in McBSP using frame length and word length 11 2 using word length and the frame sync ignore function 11 4 data receive registers DRR1 and DRR2 12 2 data reception in McBSP 2 15 data transfer process of McBSP 2 2 data transmission in McBSP 2 17 data transmit registers DXR1 and DXR2 12 3 detecting frame sync pulses 2 9 digital loopback mode receiver c...

Page 277: ...n 7 15 transmitter configuration 8 15 frame sync logic reset bit FRST described in table 12 10 shown in figure 12 4 frame sync mode receiver configuration 7 23 transmitter configuration 8 22 frame sync period bits for FSG FPER described in table 12 30 shown in figure 12 26 frame sync period for sample rate generator receiver configuration 7 29 transmitter configuration 8 27 frame sync polarity rec...

Page 278: ...ation 7 40 transmitter configuration 8 37 input clock polarity for sample rate generator 3 6 receiver configuration 7 41 transmitter configuration 8 38 interrupt mode receiver configuration 7 22 transmitter configuration 8 21 interrupts between McBSP block transfers 5 15 generated by McBSP 2 19 introduction to McBSP 1 1 J justification of receive data 7 20 K key features of McBSP 1 2 L LSB first o...

Page 279: ... of an RCER described in table 12 46 shown in figure 12 46 RCERA RCERH 12 46 RCOMPAND bits of RCR2 described in table 12 17 shown in figure 12 13 RCR1 and RCR2 12 13 RDATDLY bits of RCR2 described in table 12 18 shown in figure 12 13 reassigning blocks during reception transmission 5 6 receive channel enable registers RCERA RCERH 12 46 receive clock mode 7 31 receive clock mode bit CLKRM described...

Page 280: ...n in figure 12 31 receive phase number bit RPHASE described in table 12 16 shown in figure 12 13 receive sign extension and justification mode 7 20 receive sign extension and justification mode bits RJUST described in table 12 5 shown in figure 12 4 receive word length 7 11 receive word length 1 bits RWDLEN1 described in table 12 15 shown in figure 12 13 receive word length 2 bits RWDLEN2 describe...

Page 281: ...e rate generator 3 2 clock divide down value receiver configuration 7 37 transmitter configuration 8 34 clock mode input clock selection receiver configuration 7 40 transmitter configuration 8 37 clock synchronization mode receiver configuration 7 39 transmitter configuration 8 36 clocking examples 3 14 frame sync period and pulse width introduced 3 9 receiver configuration 7 29 transmitter config...

Page 282: ...data delay 8 17 transmit data delay bits XDATDLY described in table 12 24 shown in figure 12 19 transmit DMA event signal XEVT 2 19 transmit DX delay enabler mode 8 20 transmit frame length 8 13 transmit frame length 1 bits XFRLEN1 described in table 12 20 shown in figure 12 19 transmit frame length 2 bits XFRLEN2 described in table 12 22 shown in figure 12 19 transmit frame phase s 8 10 transmit ...

Page 283: ... 12 W word length s receiver configuration 7 11 transmitter configuration 8 11 words per frame 2 11 worksheet for McBSP registers 13 1 X XCBLK bits of MCR2 described in table 12 37 shown in figure 12 31 XCE0 XCE15 bits of an XCER described in table 12 50 shown in figure 12 49 XCERA XCERH 12 49 XCOMPAND bits of XCR2 described in table 12 23 shown in figure 12 19 XCR1 and XCR2 12 19 XDATDLY bits of ...

Page 284: ...bed in table 12 12 shown in figure 12 4 XRST bit of SPCR2 described in table 12 12 shown in figure 12 4 XSYNCERR bit of SPCR2 described in table 12 11 shown in figure 12 4 XWDLEN1 bits of XCR1 described in table 12 21 shown in figure 12 19 XWDLEN2 bits of XCR2 described in table 12 23 shown in figure 12 19 ...

Page 285: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

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