Texas Instruments TMS320VC5509, Reference Manual

Page: 38 / 285

McBSP Reception
2-15 McBSP Operation SPRU592E
2.5 McBSP Reception
This section explains the fundamental process of reception in the McBSP. For
more details on how to configure the receiver, see Chapter 7,
Receiver
Configuration .
Figure 2 − 11 and Figure 2 − 12 show how reception occurs in the McBSP.
Figure 2 − 11 shows the physical path for the data. Figure 2 − 12 is a timing
diagram showing signal activity for one possible reception scenario. A
description of the process follows the figures.
Figure 2 − 11.McBSP Reception Physical Data Path
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
DR
RSR[1,2]
Expand
ÁÁÁÁ
ÁÁÁÁ
RBR[1,2] DRR[1,2] DRR[1,2] RBR[1,2]
To CPU or
DMA controller
Justify and bit fill
or
RSR[1,2]: Receive shift registers 1 and 2
RBR[1,2]: Receive buffer registers 1 and 2 DRR[1,2]: Data receive registers 1 and 2
Figure 2 − 12. McBSP Reception Signal Activity
RRDY
DR
FSR
CLKR
Read from DRR1(b) RBR1 to DRR1 copy(B) Read from DRR1(A) RBR1 to DRR1 copy(A)
C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1
ÁÁ
ÁÁ
Á
Á
Á
Á
ÁÁ
ÁÁ
CLKR: Internal receive clock
FSR: Internal receive frame-sync signal DR: Data on DR pin
RRDY: Status of receiver ready bit
The following process describes how data travels from the DR pin to the CPU
or to the DMA controller:
1) The McBSP waits for a receive frame-sync pulse on internal FSR.
2) When the pulse arrives, the McBSP inserts the appropriate data delay that
is selected with the RDATDLY bits of RCR2.
In the preceding timing diagram (Figure 2
− 12), a 1-bit data delay is
selected.
3) The McBSP accepts data bits on the DR pin and shifts them into the
receive shift register(s).
If the word length is 16 bits or smaller, only RSR1 is used. If the word length
is larger than 16 bits, RSR2 and RSR1 are used, and RSR2 contains the
most significant bits.