![background image](http://html.mh-extra.com/html/texas-instruments/tms320vc5509/tms320vc5509_reference-manual_1094769237.webp)
Sample Rate Generator Registers (SRGR1 and SRGR2)
McBSP Registers
12-30
SPRU592E
8. SRGR2 Bit Descriptions (Continued)
Bit
Description
Description
Value
Field
12
FSGM
Sample rate generator transmit frame-sync mode bit. The transmitter can
get frame synchronization from the FSX pin (FSXM = 0) or from inside the
McBSP (FSXM = 1). When FSXM = 1, the FSGM bit determines how the
McBSP supplies frame-sync pulses.
0
If FSXM = 1, the McBSP generates a transmit frame-sync pulse when the
content of DXR[1,2] is copied to XSR[1,2].
1
If FSXM = 1, the transmitter uses frame-sync pulses generated by the
sample rate generator. Program the FWID bits to set the width of each
pulse. Program the FPER bits to set the period between pulses.
11–0
FPER
0–4095 Frame-sync period bits for FSG. The sample rate generator can produce a
clock signal, CLKG, and a frame-sync signal, FSG. The period between
frame-sync pulses on FSG is (FPER + 1) CLKG cycles. The 12 bits of
FPER allow a frame-sync period of 1 to 4096 CLKG cycles:
0
≤
FPER
≤
4095
1
≤
(FPER + 1)
≤
4096 CLKG cycles
The width of each frame-sync pulse on FSG is defined by the FWID bits.
Summary of Contents for TMS320VC5509
Page 5: ...vi This page is intentionally left blank ...
Page 43: ...McBSP Operation 2 20 SPRU592E This page is intentionally left blank ...
Page 105: ...SPI Operation Using the Clock Stop Mode 6 16 SPRU592E This page is intentionally left blank ...
Page 187: ...Transmitter Configuration 8 40 SPRU592E This page is intentionally left blank ...
Page 191: ...General Purpose I O on the McBSP Pins 9 4 SPRU592E This page is intentionally left blank ...
Page 201: ...Emulation Power and Reset Considerations 10 10 SPRU592E ...
Page 207: ...Data Packing Examples 11 6 SPRU592E This page is intentionally left blank ...
Page 273: ...McBSP Register Worksheet 13 14 SPRU592E This page is intentionally left blank ...