Texas Instruments TMS320VC5509, Reference Manual

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Data Receive Registers (DRR1 and DRR2)
McBSP Registers 12-2 SPRU592E
12.1 Data Receive Registers (DRR1 and DRR2)
The CPU or the DMA controller reads received data from one or both of the
data receive registers (see Figure 12
− 1). If the serial word length is 16 bits or
smaller only DRR1 is used. If the serial length is larger than 16 bits, both DRR1
and DRR2 are used, and DRR2 holds the most significant bits. Each frame of
receive data in the McBSP can have one phase or two phases, each with its
own serial word length.
DRR1 and DRR2 are I/O mapped registers; they are accessible at addresses
in I/O space.
Figure 12 − 1. Data Receive Registers (DRR1 and DRR2)
DRR2
15 0
High part of receive data (for 20-, 24- or 32-bit data)
R/W-0
DRR1
15 0
Receive data (for 8-, 12-, or 16-bit data) or Low part of receive data (for 20-, 24- or 32-bit data)
R/W-0
Legend: R = Read; W = Write; - n = Value after reset
12.1.1 How Data Travels From the Data Receive (DR) Pin to the DRRs
If the serial word length is 16 bits or smaller, receive data on the DR pin is
shifted into receive shift register 1 (RSR1) and then copied into receive buffer
register 1 (RBR1). The content of RBR1 is then copied to DRR1, which can be
read by the CPU or by the DMA controller.
If the serial word length is larger than 16 bits, receive data on the DR pin is
shifted into both of the receive shift registers (RSR2, RSR1) and then copied
into both of the receive buffer registers (RBR2, RBR1). The content of the
RBRs is then copied into both of the DRRs, which can be read by the CPU or
by the DMA controller.
If companding is used during the copy from RBR1 to DRR1
(RCOMPAND = 10b or 11b), the 8-bit compressed data in RBR1 is expanded
to a left-justified 16-bit value in DRR1. If companding is disabled, the data
copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the
RJUST bits.
The RSRs and RBRs are not accessible. They are not mapped to I/O space
like the DRRs.