Texas Instruments TMS320VC5509, Reference Manual, Page: 198 / 285

Resetting and Initializing a McBSP
10-7 Emulation, Power, and Reset Considerations SPRU592E
4) Set GRST = 1 to enable the sample rate generator.
5) Wait for two clock cycles. This ensures proper internal synchronization.
6) Set up data acquisition as required (such as writing to DXR[1,2]).
7) Make XRST = RRST = 1 to enable the serial port. Make sure that as you
set these reset bits, you do not modify any of the other bits in SPCR1 and
SPCR2. Otherwise, you will change the configuration you selected in
step 2.
8) Set FRST = 1, if internally generated frame synchronization is required.
9) Wait two clock cycles for the receiver and transmitter to become active.
Alternatively, on either write (step 1 or 5), the transmitter and receiver can be
placed in or taken out of reset individually by a modification of the desired bit.
The above procedure for reset/initialization can be applied in general when the
receiver or transmitter has to be reset during its normal operation, and also
when the sample rate generator is not used for either operation.
Notes:
1) The necessary duration of the active-low period of XRST or RRST is at
least two CLKR/CLKX cycles.
2) The appropriate bits in serial port configuration registers SPCR[1,2],
PCR, RCR[1,2], XCR[1,2], and SRGR[1,2] should only be modified
when the affected portion of the serial port is in its reset state.
3) In most cases, the data transmit registers (DXR[1,2]) should be loaded
by the CPU or by the DMA controller only when the transmitter is enabled
(XRST = 1). An exception to this rule is when these registers are used
for companding internal data.
4) The bits of the channel control registers, MCR[1,2], RCER[A–H], and
XCER[A–H], can be modified at any time as long as they are not being
used by the current reception/transmission in a multichannel selection
mode.