Multichannel Control Registers (MCR1 and MCR2)
McBSP Registers
12-32
SPRU592E
Table 12
−
9. MCR1 Bit Descriptions
Bit
Field
Value
Description
15-10
Reserved
0
Reserved bits (not available for your use). They are read-only bits and
return 0s when read.
9
RMCME
Receive multichannel partition mode bit. RMCME is only applicable if
channels can be individually enabled or disabled for reception (RMCM = 1).
RMCME determines whether only 32 channels or all 128 channels are to
be individually selectable.
0
2-partition mode
Only partitions A and B are used. You can control up to 32 channels in the
receive multichannel selection mode (RMCM = 1).
Assign 16 channels to partition A with the RPABLK bits. Assign 16 channels
to partition B with the RPBBLK bits.
You control the channels with the appropriate receive channel enable
registers:
RCERA: Channels in partition A
RCERB: Channels in partition B
1
8-partition mode
All partitions (A through H) are used. You can control up to 128 channels in
the receive multichannel selection mode.
You control the channels with the appropriate receive channel enable
registers:
RCERA: Channels 0 through 15
RCERB: Channels 16 through 31
RCERC: Channels 32 through 47
RCERD: Channels 48 through 63
RCERE: Channels 64 through 79
RCERF: Channels 80 through 95
RCERG: Channels 96 through 111
RCERH: Channels 112 through 127
Summary of Contents for TMS320VC5509
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Page 43: ...McBSP Operation 2 20 SPRU592E This page is intentionally left blank ...
Page 105: ...SPI Operation Using the Clock Stop Mode 6 16 SPRU592E This page is intentionally left blank ...
Page 187: ...Transmitter Configuration 8 40 SPRU592E This page is intentionally left blank ...
Page 191: ...General Purpose I O on the McBSP Pins 9 4 SPRU592E This page is intentionally left blank ...
Page 201: ...Emulation Power and Reset Considerations 10 10 SPRU592E ...
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