Tegam 2411B, Operation Manual

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Chapter 8 Advanced Programming
GPIB (IEEE-488.2) Overview - Status and Event Registers (continued)
Status and Event Registers (continued)
ESR and ESE Registers - Each bit of the 8 bit ESR Register indicates a different condition within the
device. The ESE Register provides a bit by bit mask of the ESR register. When a bit in the ESE Register
is set TRUE, it enables the corresponding ESR bit to generate a Service Request (SRQ), if the
Standard Event bit (bit 5) in the SRE Register has also been enabled.
For example, if you wanted to generate an SRQ on
1) power on (bit 7)
2) command error (bit 5)
3) query error (bit 2)
you would first set the ESB bit in the SRE Register (see discussion below) and then send the following:
*ESE 164 (164 = decimal equivalent of binary 10100100)
The *ESE? and *ESR? command queries allow reading of the Standard Event Status Enable and
Standard Event Status Registers, respectively.
SRE and STB Registers - The Status Byte (STB) Register of the 2411B has four active bits which
summarize the current status of the event registers, output queue, and certain instrument specific func-
tions. Similar to the ESE Register, the SRE Register provides an 8-bit mask to allow the programmer to
enable each STB bit (with the exception of the bit 6) to generate an SRQ.
As an example, to enable the Standard Event and Message Available bits, but not the Device Dependent
(bit 0), of the Status Byte Register, you would send the following command:
*SRE 48 (48 = Decimal equivalent of B00110000)
The *SRE? and *STB? command queries allow reading of the Service Request Enable and Status Byte
Registers, respectively.
The Device Dependent bit (bit 0) or USR0 is user-defined, and summarizes the instrument status regis-
ters.
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